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FPGA向SRAM中写入数据

Cell Usage :
# BELS                             : 168
#      GND                         : 1
#      LUT1                        : 20
#      LUT1_D                      : 1
#      LUT1_L                      : 16
#      LUT2                        : 6
#      LUT2_D                      : 3
#      LUT3                        : 1
#      LUT3_L                      : 1
#      LUT4                        : 32
#      LUT4_L                      : 22
#      MUXCY                       : 32
#      VCC                         : 1
#      XORCY                       : 32
# FlipFlops/Latches                : 67
#      FD                          : 12
#      FDE                         : 24
#      FDRE                        : 28
#      FDSE                        : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 31
#      IBUF                        : 1
#      OBUF                        : 30
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      58  out of   3584     1%  
 Number of Slice Flip Flops:            67  out of   7168     0%  
 Number of 4 input LUTs:               102  out of   7168     1%  
 Number of bonded IOBs:                 31  out of    141    21%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 12    |
count_10_1:Q                       | NONE                   | 28    |
count_10:Q                         | NONE                   | 27    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 1.914ns (Maximum Frequency: 522.466MHz)
   Minimum input arrival time before clock: 3.103ns
   Maximum output required time after clock: 6.357ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               1.317ns (Levels of Logic = 2)
  Source:            count_10 (FF)
  Destination:       count_10 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: count_10 to count_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              28   0.000   1.317  count_10 (count_10)
     LUT1:I0->O            0   0.000   0.000  count<10>_rt (count<10>_rt)
     XORCY:LI->O           2   0.000   0.000  count_Madd__n0000_inst_sum_34 (count__n0000<10>)
     FD:D                      0.000          count_10
    ----------------------------------------
    Total                      1.317ns (0.000ns logic, 1.317ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'count_10_1:Q'
Delay:               1.914ns (Levels of Logic = 1)
  Source:            is_end (FF)
  Destination:       data_SRAM_7 (FF)
  Source Clock:      count_10_1:Q rising
  Destination Clock: count_10_1:Q rising

  Data Path: is_end to data_SRAM_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             9   0.000   0.777  is_end (is_end)
     LUT2:I1->O           20   0.000   1.137  addr_SRAM_N1841_4 (addr_SRAM_N1841_4)
     FDE:CE                    0.000          data_SRAM_7
    ----------------------------------------
    Total                      1.914ns (0.000ns logic, 1.914ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'count_10:Q'
Delay:               0.817ns (Levels of Logic = 3)
  Source:            data_in_7 (FF)
  Destination:       data_in_7 (FF)
  Source Clock:      count_10:Q rising
  Destination Clock: count_10:Q rising

  Data Path: data_in_7 to data_in_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.000   0.577  data_in_7 (data_in_7)
     LUT1:I0->O            0   0.000   0.000  data_in<7>_rt (data_in<7>_rt)
     XORCY:LI->O           1   0.000   0.240  Madd__n0013_inst_sum_7 (_n0013<7>)
     LUT4:I1->O            1   0.000   0.000  _n0005<7>1 (_n0005<7>)
     FDRE:D                    0.000          data_in_7
    ----------------------------------------
    Total                      0.817ns (0.000ns logic, 0.817ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'count_10_1:Q'
Offset:              3.103ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       data_SRAM_7 (FF)
  Destination Clock: count_10_1:Q rising

  Data Path: reset to data_SRAM_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            36   0.641   1.325  reset_IBUF (reset_IBUF)
     LUT2:I0->O           20   0.000   1.137  addr_SRAM_N1841_4 (addr_SRAM_N1841_4)
     FDE:CE                    0.000          data_SRAM_7
    ----------------------------------------
    Total                      3.103ns (0.641ns logic, 2.462ns route)
                                       (20.7% logic, 79.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'count_10:Q'
Offset:              3.103ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       addr_SRAM_15 (FF)
  Destination Clock: count_10:Q rising

  Data Path: reset to addr_SRAM_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            36   0.641   1.325  reset_IBUF (reset_IBUF)
     LUT2:I0->O           20   0.000   1.137  addr_SRAM_N1841_4 (addr_SRAM_N1841_4)
     FDE:CE                    0.000          data_SRAM_2
    ----------------------------------------
    Total                      3.103ns (0.641ns logic, 2.462ns route)
                                       (20.7% logic, 79.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'count_10_1:Q'
Offset:              6.357ns (Levels of Logic = 1)
  Source:            is_end (FF)
  Destination:       led (PAD)
  Source Clock:      count_10_1:Q rising

  Data Path: is_end to led
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             9   0.000   0.777  is_end (is_end)
     OBUF:I->O                 5.580          led_OBUF (led)
    ----------------------------------------
    Total                      6.357ns (5.580ns logic, 0.777ns route)
                                       (87.8% logic, 12.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'count_10:Q'
Offset:              6.045ns (Levels of Logic = 1)
  Source:            data_SRAM_2 (FF)
  Destination:       data_SRAM<2> (PAD)
  Source Clock:      count_10:Q rising

  Data Path: data_SRAM_2 to data_SRAM<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.000   0.465  data_SRAM_2 (data_SRAM_2)
     OBUF:I->O                 5.580          data_SRAM_2_OBUF (data_SRAM<2>)
    ----------------------------------------
    Total                      6.045ns (5.580ns logic, 0.465ns route)
                                       (92.3% logic, 7.7% route)

=========================================================================
CPU : 8.86 / 12.92 s | Elapsed : 8.00 / 12.00 s
 
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Total memory usage is 71228 kilobytes