csl_emifahal.h

基于DM642的视频回放源码

  #define  EMIFA_CECTL_WRSTRB_DEFAULT   0x0000003Fu
  #define  EMIFA_CECTL_WRSTRB_OF(x)     _VALUEOF(x)

  #define _EMIFA_CECTL_WRHLD_MASK       0x00300000u
  #define _EMIFA_CECTL_WRHLD_SHIFT      0x00000014u
  #define  EMIFA_CECTL_WRHLD_DEFAULT    0x00000003u
  #define  EMIFA_CECTL_WRHLD_OF(x)      _VALUEOF(x)
  
  #define _EMIFA_CECTL_RDSETUP_MASK     0x000F0000u
  #define _EMIFA_CECTL_RDSETUP_SHIFT    0x00000010u
  #define  EMIFA_CECTL_RDSETUP_DEFAULT  0x0000000Fu
  #define  EMIFA_CECTL_RDSETUP_OF(x)    _VALUEOF(x)

  #define _EMIFA_CECTL_TA_MASK          0x0000C000u
  #define _EMIFA_CECTL_TA_SHIFT         0x0000000Eu
  #define  EMIFA_CECTL_TA_DEFAULT       0x00000003u
  #define  EMIFA_CECTL_TA_OF(x)         _VALUEOF(x)

  #define _EMIFA_CECTL_RDSTRB_MASK      0x00003F00u
  #define _EMIFA_CECTL_RDSTRB_SHIFT     0x00000008u
  #define  EMIFA_CECTL_RDSTRB_DEFAULT   0x0000003Fu
  #define  EMIFA_CECTL_RDSTRB_OF(x)     _VALUEOF(x)
  
  #define _EMIFA_CECTL_MTYPE_MASK       0x000000F0u
  #define _EMIFA_CECTL_MTYPE_SHIFT      0x00000004u
  #define  EMIFA_CECTL_MTYPE_DEFAULT    0x00000000u
  #define  EMIFA_CECTL_MTYPE_OF(x)      _VALUEOF(x)
  #define  EMIFA_CECTL_MTYPE_ASYNC8     0x00000000u
  #define  EMIFA_CECTL_MTYPE_ASYNC16    0x00000001u
  #define  EMIFA_CECTL_MTYPE_ASYNC32    0x00000002u
  #define  EMIFA_CECTL_MTYPE_SDRAM32    0x00000003u
  #define  EMIFA_CECTL_MTYPE_SYNC32     0x00000004u
  #define  EMIFA_CECTL_MTYPE_SDRAM8     0x00000008u
  #define  EMIFA_CECTL_MTYPE_SDRAM16    0x00000009u
  #define  EMIFA_CECTL_MTYPE_SYNC8      0x0000000Au
  #define  EMIFA_CECTL_MTYPE_SYNC16     0x0000000Bu
#if (!(CHIP_6410 || CHIP_6413 || CHIP_6418 ))
  #define  EMIFA_CECTL_MTYPE_ASYNC64    0x0000000Cu
  #define  EMIFA_CECTL_MTYPE_SDRAM64    0x0000000Du
  #define  EMIFA_CECTL_MTYPE_SYNC64     0x0000000Eu
#endif
  #define _EMIFA_CECTL_WRHLDMSB_MASK    0x00000008u
  #define _EMIFA_CECTL_WRHLDMSB_SHIFT   0x00000003u
  #define  EMIFA_CECTL_WRHLDMSB_DEFAULT 0x00000000u
  #define  EMIFA_CECTL_WRHLDMSB_OF(x)   _VALUEOF(x)

  #define _EMIFA_CECTL_RDHLD_MASK       0x00000007u
  #define _EMIFA_CECTL_RDHLD_SHIFT      0x00000000u
  #define  EMIFA_CECTL_RDHLD_DEFAULT    0x00000003u
  #define  EMIFA_CECTL_RDHLD_OF(x)      _VALUEOF(x)

  #define  EMIFA_CECTL_OF(x)            _VALUEOF(x)

  #define EMIFA_CECTL_DEFAULT (Uint32)( \
     _PER_FDEFAULT(EMIFA,CECTL,WRSETUP)\
    |_PER_FDEFAULT(EMIFA,CECTL,WRSTRB)\
    |_PER_FDEFAULT(EMIFA,CECTL,WRHLD)\
    |_PER_FDEFAULT(EMIFA,CECTL,RDSETUP)\
    |_PER_FDEFAULT(EMIFA,CECTL,TA)\
    |_PER_FDEFAULT(EMIFA,CECTL,RDSTRB)\
    |_PER_FDEFAULT(EMIFA,CECTL,MTYPE)\
    |_PER_FDEFAULT(EMIFA,CECTL,WRHLDMSB)\
    |_PER_FDEFAULT(EMIFA,CECTL,RDHLD)\
  )
#if (CHIP_6413 || CHIP_6418 || CHIP_6410)
  /*Read only field TA has a value of 0x3 */
  #define EMIFA_CECTL_RMK(wrsetup,wrstrb,wrhld,rdsetup,rdstrb,mtype,\
    wrhldmsb,rdhld) (Uint32)( \
     _PER_FMK(EMIFA,CECTL,WRSETUP,wrsetup)\
    |_PER_FMK(EMIFA,CECTL,WRSTRB,wrstrb)\
    |_PER_FMK(EMIFA,CECTL,WRHLD,wrhld)\
    |_PER_FMK(EMIFA,CECTL,TA,0x3)\
    |_PER_FMK(EMIFA,CECTL,RDSETUP,rdsetup)\
    |_PER_FMK(EMIFA,CECTL,RDSTRB,rdstrb)\
    |_PER_FMK(EMIFA,CECTL,MTYPE,mtype)\
    |_PER_FMK(EMIFA,CECTL,WRHLDMSB,wrhldmsb)\
    |_PER_FMK(EMIFA,CECTL,RDHLD,rdhld)\
  )
#else
   #define EMIFA_CECTL_RMK(wrsetup,wrstrb,wrhld,ta,rdsetup,rdstrb,mtype,\
    wrhldmsb,rdhld) (Uint32)( \
     _PER_FMK(EMIFA,CECTL,WRSETUP,wrsetup)\
    |_PER_FMK(EMIFA,CECTL,WRSTRB,wrstrb)\
    |_PER_FMK(EMIFA,CECTL,WRHLD,wrhld)\
    |_PER_FMK(EMIFA,CECTL,TA,ta)\
    |_PER_FMK(EMIFA,CECTL,RDSETUP,rdsetup)\
    |_PER_FMK(EMIFA,CECTL,RDSTRB,rdstrb)\
    |_PER_FMK(EMIFA,CECTL,MTYPE,mtype)\
    |_PER_FMK(EMIFA,CECTL,WRHLDMSB,wrhldmsb)\
    |_PER_FMK(EMIFA,CECTL,RDHLD,rdhld)\
  )  
#endif    
  #define _EMIFA_CECTL_FGET(N,FIELD)\
    _PER_FGET(_EMIFA_CECTL##N##_ADDR,EMIFA,CECTL,##FIELD)

  #define _EMIFA_CECTL_FSET(N,FIELD,f)\
    _PER_FSET(_EMIFA_CECTL##N##_ADDR,EMIFA,CECTL,##FIELD,f)

  #define _EMIFA_CECTL_FSETS(N,FIELD,SYM)\
    _PER_FSETS(_EMIFA_CECTL##N##_ADDR,EMIFA,CECTL,##FIELD,##SYM)

  #define _EMIFA_CECTL0_FGET(FIELD) _EMIFA_CECTL_FGET(0,##FIELD)
  #define _EMIFA_CECTL1_FGET(FIELD) _EMIFA_CECTL_FGET(1,##FIELD)
  #define _EMIFA_CECTL2_FGET(FIELD) _EMIFA_CECTL_FGET(2,##FIELD)
  #define _EMIFA_CECTL3_FGET(FIELD) _EMIFA_CECTL_FGET(3,##FIELD)

  #define _EMIFA_CECTL0_FSET(FIELD,f) _EMIFA_CECTL_FSET(0,##FIELD,f)
  #define _EMIFA_CECTL1_FSET(FIELD,f) _EMIFA_CECTL_FSET(1,##FIELD,f)
  #define _EMIFA_CECTL2_FSET(FIELD,f) _EMIFA_CECTL_FSET(2,##FIELD,f)
  #define _EMIFA_CECTL3_FSET(FIELD,f) _EMIFA_CECTL_FSET(3,##FIELD,f)

  #define _EMIFA_CECTL0_FSETS(FIELD,SYM) _EMIFA_CECTL_FSETS(0,##FIELD,##SYM)
  #define _EMIFA_CECTL1_FSETS(FIELD,SYM) _EMIFA_CECTL_FSETS(1,##FIELD,##SYM)
  #define _EMIFA_CECTL2_FSETS(FIELD,SYM) _EMIFA_CECTL_FSETS(2,##FIELD,##SYM)
  #define _EMIFA_CECTL3_FSETS(FIELD,SYM) _EMIFA_CECTL_FSETS(3,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  S D C T L        |
* |___________________|
*
* SDCTL   - SDRAM control regsiter
*
* FIELDS (msb -> lsb)
* (rw) SDBSZ 
* (rw) SDRSZ 
* (rw) SDCSZ 
* (rw) RFEN
* (w)  INIT
* (rw) TRCD
* (rw) TRP
* (rw) TRC
* (rw) SLFRFR
*
\******************************************************************************/
  #define _EMIFA_SDCTL_OFFSET           6

  #define _EMIFA_SDCTL_ADDR             0x01800018u

  #define _EMIFA_SDCTL_SDBSZ_MASK       0x40000000u
  #define _EMIFA_SDCTL_SDBSZ_SHIFT      0x0000001Eu
  #define  EMIFA_SDCTL_SDBSZ_DEFAULT    0x00000000u
  #define  EMIFA_SDCTL_SDBSZ_OF(x)      _VALUEOF(x)
  #define  EMIFA_SDCTL_SDBSZ_2BANKS     0x00000000u
  #define  EMIFA_SDCTL_SDBSZ_4BANKS     0x00000001u
  
  #define _EMIFA_SDCTL_SDRSZ_MASK       0x30000000u
  #define _EMIFA_SDCTL_SDRSZ_SHIFT      0x0000001Cu
  #define  EMIFA_SDCTL_SDRSZ_DEFAULT    0x00000000u
  #define  EMIFA_SDCTL_SDRSZ_OF(x)      _VALUEOF(x)
  #define  EMIFA_SDCTL_SDRSZ_11ROW      0x00000000u
  #define  EMIFA_SDCTL_SDRSZ_12ROW      0x00000001u
  #define  EMIFA_SDCTL_SDRSZ_13ROW      0x00000002u
  
  #define _EMIFA_SDCTL_SDCSZ_MASK       0x0C000000u
  #define _EMIFA_SDCTL_SDCSZ_SHIFT      0x0000001Au
  #define  EMIFA_SDCTL_SDCSZ_DEFAULT    0x00000000u
  #define  EMIFA_SDCTL_SDCSZ_OF(x)      _VALUEOF(x)
  #define  EMIFA_SDCTL_SDCSZ_9COL       0x00000000u
  #define  EMIFA_SDCTL_SDCSZ_8COL       0x00000001u
  #define  EMIFA_SDCTL_SDCSZ_10COL      0x00000002u
  
  #define _EMIFA_SDCTL_RFEN_MASK        0x02000000u
  #define _EMIFA_SDCTL_RFEN_SHIFT       0x00000019u
  #define  EMIFA_SDCTL_RFEN_DEFAULT     0x00000001u
  #define  EMIFA_SDCTL_RFEN_OF(x)       _VALUEOF(x)
  #define  EMIFA_SDCTL_RFEN_DISABLE     0x00000000u
  #define  EMIFA_SDCTL_RFEN_ENABLE      0x00000001u

  #define _EMIFA_SDCTL_INIT_MASK        0x01000000u
  #define _EMIFA_SDCTL_INIT_SHIFT       0x00000018u
  #define  EMIFA_SDCTL_INIT_DEFAULT     0x00000001u
  #define  EMIFA_SDCTL_INIT_OF(x)       _VALUEOF(x)
  #define  EMIFA_SDCTL_INIT_NO          0x00000000u
  #define  EMIFA_SDCTL_INIT_YES         0x00000001u

  #define _EMIFA_SDCTL_TRCD_MASK        0x00F00000u
  #define _EMIFA_SDCTL_TRCD_SHIFT       0x00000014u
  #define  EMIFA_SDCTL_TRCD_DEFAULT     0x00000004u
  #define  EMIFA_SDCTL_TRCD_OF(x)       _VALUEOF(x)

  #define _EMIFA_SDCTL_TRP_MASK         0x000F0000u
  #define _EMIFA_SDCTL_TRP_SHIFT        0x00000010u
  #define  EMIFA_SDCTL_TRP_DEFAULT      0x00000008u
  #define  EMIFA_SDCTL_TRP_OF(x)        _VALUEOF(x)

  #define _EMIFA_SDCTL_TRC_MASK         0x0000F000u
  #define _EMIFA_SDCTL_TRC_SHIFT        0x0000000Cu
  #define  EMIFA_SDCTL_TRC_DEFAULT      0x0000000Fu
  #define  EMIFA_SDCTL_TRC_OF(x)        _VALUEOF(x)

  #define _EMIFA_SDCTL_SLFRFR_MASK      0x00000001u
  #define _EMIFA_SDCTL_SLFRFR_SHIFT     0x00000000u
  #define  EMIFA_SDCTL_SLFRFR_DEFAULT   0x00000000u
  #define  EMIFA_SDCTL_SLFRFR_OF(x)     _VALUEOF(x)
  #define  EMIFA_SDCTL_SLFRFR_DISABLE   0x00000000u
  #define  EMIFA_SDCTL_SLFRFR_ENABLE    0x00000001u

  #define  EMIFA_SDCTL_OF(x)            _VALUEOF(x)

  #define EMIFA_SDCTL_DEFAULT (Uint32)( \
     _PER_FDEFAULT(EMIFA,SDCTL,SDBSZ)\
    |_PER_FDEFAULT(EMIFA,SDCTL,SDRSZ)\
    |_PER_FDEFAULT(EMIFA,SDCTL,SDCSZ)\
    |_PER_FDEFAULT(EMIFA,SDCTL,RFEN)\
    |_PER_FDEFAULT(EMIFA,SDCTL,INIT)\
    |_PER_FDEFAULT(EMIFA,SDCTL,TRCD)\
    |_PER_FDEFAULT(EMIFA,SDCTL,TRP)\
    |_PER_FDEFAULT(EMIFA,SDCTL,TRC)\
    |_PER_FDEFAULT(EMIFA,SDCTL,SLFRFR)\
  )

  #define EMIFA_SDCTL_RMK(sdbsz,sdrsz,sdcsz,rfen,init,trcd,trp,trc,slfrfr) (Uint32)(\
     _PER_FMK(EMIFA,SDCTL,SDBSZ,sdbsz)\
    |_PER_FMK(EMIFA,SDCTL,SDRSZ,sdrsz)\
    |_PER_FMK(EMIFA,SDCTL,SDCSZ,sdcsz)\
    |_PER_FMK(EMIFA,SDCTL,RFEN,rfen)\
    |_PER_FMK(EMIFA,SDCTL,INIT,init)\
    |_PER_FMK(EMIFA,SDCTL,TRCD,trcd)\
    |_PER_FMK(EMIFA,SDCTL,TRP,trp)\
    |_PER_FMK(EMIFA,SDCTL,TRC,trc)\
    |_PER_FMK(EMIFA,SDCTL,SLFRFR,slfrfr)\
  )

  #define _EMIFA_SDCTL_FGET(FIELD)\
    _PER_FGET(_EMIFA_SDCTL_ADDR,EMIFA,SDCTL,##FIELD)

  #define _EMIFA_SDCTL_FSET(FIELD,field)\
    _PER_FSET(_EMIFA_SDCTL_ADDR,EMIFA,SDCTL,##FIELD,field)

  #define _EMIFA_SDCTL_FSETS(FIELD,SYM)\
    _PER_FSETS(_EMIFA_SDCTL_ADDR,EMIFA,SDCTL,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  S D T I M        |
* |___________________|
*
* SDTIM   - SDRAM timing register
*
* FIELDS (msb -> lsb)
* (rw) XRFR
* (r)  CNTR
* (rw) PERIOD
*
\******************************************************************************/
  #define _EMIFA_SDTIM_OFFSET           7

  #define _EMIFA_SDTIM_ADDR             0x0180001Cu

  #define _EMIFA_SDTIM_XRFR_MASK        0x03000000u
  #define _EMIFA_SDTIM_XRFR_SHIFT       0x00000018u
  #define  EMIFA_SDTIM_XRFR_DEFAULT     0x00000000u
  #define  EMIFA_SDTIM_XRFR_OF(x)       _VALUEOF(x)

  #define _EMIFA_SDTIM_CNTR_MASK        0x00FFF000u
  #define _EMIFA_SDTIM_CNTR_SHIFT       0x0000000Cu
  #define  EMIFA_SDTIM_CNTR_DEFAULT     0x000005DCu
  #define  EMIFA_SDTIM_CNTR_OF(x)       _VALUEOF(x)
  
  #define _EMIFA_SDTIM_PERIOD_MASK      0x00000FFFu
  #define _EMIFA_SDTIM_PERIOD_SHIFT     0x00000000u
  #define  EMIFA_SDTIM_PERIOD_DEFAULT   0x000005DCu
  #define  EMIFA_SDTIM_PERIOD_OF(x)     _VALUEOF(x)

  #define  EMIFA_SDTIM_OF(x)            _VALUEOF(x)

  #define EMIFA_SDTIM_DEFAULT (Uint32)( \
     _PER_FDEFAULT(EMIFA,SDTIM,XRFR)\
    |_PER_FDEFAULT(EMIFA,SDTIM,CNTR)\
    |_PER_FDEFAULT(EMIFA,SDTIM,PERIOD)\
  )

  #define EMIFA_SDTIM_RMK(xrfr,period) (Uint32)(\
     _PER_FMK(EMIFA,SDTIM,XRFR,xrfr)\
    |_PER_FMK(EMIFA,SDTIM,PERIOD,period)\
  )

  #define _EMIFA_SDTIM_FGET(FIELD)\
    _PER_FGET(_EMIFA_SDTIM_ADDR,EMIFA,SDTIM,##FIELD)

  #define _EMIFA_SDTIM_FSET(FIELD,field)\
    _PER_FSET(_EMIFA_SDTIM_ADDR,EMIFA,SDTIM,##FIELD,field)

  #define _EMIFA_SDTIM_FSETS(FIELD,SYM)\
    _PER_FSETS(_EMIFA_SDTIM_ADDR,EMIFA,SDTIM,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  S D E X T        |
* |___________________|
*
* SDEXT   - SDRAM extension register