📄 csl_emifahal.h
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/******************************************************************************\* Copyright (C) 2001 Texas Instruments Incorporated.* All Rights Reserved*------------------------------------------------------------------------------* FILENAME...... csl_emifahal.h* DATE CREATED.. 03/27/2001 * LAST MODIFIED. 08/02/2004 - Adding support for C6418* 03/27/2001* 04/16/2004 Added PDTCTL register support *------------------------------------------------------------------------------* REGISTERS** GBLCTL - global control register* CECTL0 - CE space control register 0* CECTL1 - CE space control register 1* CECTL2 - CE space control register 2* CECTL3 - CE space control register 3* SDCTL - SDRAM control regsiter* SDTIM - SDRAM timing register* SDEXT - SDRAM extension register * CESEC0 - EMIFA CE0 secondary control * CESEC1 - EMIFA CE1 secondary control * CESEC2 - EMIFA CE2 secondary control * CESEC3 - EMIFA CE3 secondary control * PDTCTL - Peripheral device transfer control *\******************************************************************************/#ifndef _CSL_EMIFAHAL_H_#define _CSL_EMIFAHAL_H_#include <csl_stdinc.h>#include <csl_chip.h>#if (EMIFA_SUPPORT)/******************************************************************************\* MISC section\******************************************************************************/#define _EMIFA_BASE_GLOBAL 0x01800000u/******************************************************************************\* module level register/field access macros\******************************************************************************/ /* ----------------- */ /* FIELD MAKE MACROS */ /* ----------------- */ #define EMIFA_FMK(REG,FIELD,x)\ _PER_FMK(EMIFA,##REG,##FIELD,x) #define EMIFA_FMKS(REG,FIELD,SYM)\ _PER_FMKS(EMIFA,##REG,##FIELD,##SYM) /* -------------------------------- */ /* RAW REGISTER/FIELD ACCESS MACROS */ /* -------------------------------- */ #define EMIFA_ADDR(REG)\ _EMIFA_##REG##_ADDR #define EMIFA_RGET(REG)\ _PER_RGET(_EMIFA_##REG##_ADDR,EMIFA,##REG) #define EMIFA_RSET(REG,x)\ _PER_RSET(_EMIFA_##REG##_ADDR,EMIFA,##REG,x) #define EMIFA_FGET(REG,FIELD)\ _EMIFA_##REG##_FGET(##FIELD) #define EMIFA_FSET(REG,FIELD,x)\ _EMIFA_##REG##_FSET(##FIELD,##x) #define EMIFA_FSETS(REG,FIELD,SYM)\ _EMIFA_##REG##_FSETS(##FIELD,##SYM) /* ------------------------------------------ */ /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ /* ------------------------------------------ */ #define EMIFA_RGETA(addr,REG)\ _PER_RGET(addr,EMIFA,##REG) #define EMIFA_RSETA(addr,REG,x)\ _PER_RSET(addr,EMIFA,##REG,x) #define EMIFA_FGETA(addr,REG,FIELD)\ _PER_FGET(addr,EMIFA,##REG,##FIELD) #define EMIFA_FSETA(addr,REG,FIELD,x)\ _PER_FSET(addr,EMIFA,##REG,##FIELD,x) #define EMIFA_FSETSA(addr,REG,FIELD,SYM)\ _PER_FSETS(addr,EMIFA,##REG,##FIELD,##SYM)/******************************************************************************\* _____________________* | |* | G B L C T L |* |___________________|** GBLCTL - global control register** FIELDS (msb -> lsb)* (rw) EK2RATE* (rw) EK2HZ* (rw) EK2EN* (rw) BRMODE* (r) BUSREQ* (r) ARDY* (r) HOLD* (r) HOLDA* (rw) NOHOLD* (rw) EK1HZ* (rw) EK1EN* (rw) CLK4EN* (rw) CLK6EN*\******************************************************************************/ #define _EMIFA_GBLCTL_OFFSET 0 #define _EMIFA_GBLCTL_ADDR 0x01800000u #define _EMIFA_GBLCTL_EK2RATE_MASK 0x000C0000u #define _EMIFA_GBLCTL_EK2RATE_SHIFT 0x00000012u #define EMIFA_GBLCTL_EK2RATE_DEFAULT 0x00000002u #define EMIFA_GBLCTL_EK2RATE_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_EK2RATE_FULLCLK 0x00000000u #define EMIFA_GBLCTL_EK2RATE_HALFCLK 0x00000001u #define EMIFA_GBLCTL_EK2RATE_QUARCLK 0x00000002u #define _EMIFA_GBLCTL_EK2HZ_MASK 0x00020000u #define _EMIFA_GBLCTL_EK2HZ_SHIFT 0x00000011u #define EMIFA_GBLCTL_EK2HZ_DEFAULT 0x00000000u #define EMIFA_GBLCTL_EK2HZ_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_EK2HZ_CLK 0x00000000u #define EMIFA_GBLCTL_EK2HZ_HIGHZ 0x00000001u #define _EMIFA_GBLCTL_EK2EN_MASK 0x00010000u #define _EMIFA_GBLCTL_EK2EN_SHIFT 0x00000010u #define EMIFA_GBLCTL_EK2EN_DEFAULT 0x00000001u #define EMIFA_GBLCTL_EK2EN_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_EK2EN_DISABLE 0x00000000u #define EMIFA_GBLCTL_EK2EN_ENABLE 0x00000001u #define _EMIFA_GBLCTL_BRMODE_MASK 0x00002000u #define _EMIFA_GBLCTL_BRMODE_SHIFT 0x0000000Du #define EMIFA_GBLCTL_BRMODE_DEFAULT 0x00000001u #define EMIFA_GBLCTL_BRMODE_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_BRMODE_MSTATUS 0x00000000u #define EMIFA_GBLCTL_BRMODE_MRSTATUS 0x00000001u #define _EMIFA_GBLCTL_BUSREQ_MASK 0x00000800u #define _EMIFA_GBLCTL_BUSREQ_SHIFT 0x0000000Bu #define EMIFA_GBLCTL_BUSREQ_DEFAULT 0x00000000u #define EMIFA_GBLCTL_BUSREQ_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_BUSREQ_LOW 0x00000000u #define EMIFA_GBLCTL_BUSREQ_HIGH 0x00000001u #define _EMIFA_GBLCTL_ARDY_MASK 0x00000400u #define _EMIFA_GBLCTL_ARDY_SHIFT 0x0000000Au #define EMIFA_GBLCTL_ARDY_DEFAULT 0x00000000u #define EMIFA_GBLCTL_ARDY_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_ARDY_LOW 0x00000000u #define EMIFA_GBLCTL_ARDY_HIGH 0x00000001u #define _EMIFA_GBLCTL_HOLD_MASK 0x00000200u #define _EMIFA_GBLCTL_HOLD_SHIFT 0x00000009u #define EMIFA_GBLCTL_HOLD_DEFAULT 0x00000000u #define EMIFA_GBLCTL_HOLD_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_HOLD_LOW 0x00000000u #define EMIFA_GBLCTL_HOLD_HIGH 0x00000001u #define _EMIFA_GBLCTL_HOLDA_MASK 0x00000100u #define _EMIFA_GBLCTL_HOLDA_SHIFT 0x00000008u #define EMIFA_GBLCTL_HOLDA_DEFAULT 0x00000000u #define EMIFA_GBLCTL_HOLDA_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_HOLDA_LOW 0x00000000u #define EMIFA_GBLCTL_HOLDA_HIGH 0x00000001u #define _EMIFA_GBLCTL_NOHOLD_MASK 0x00000080u #define _EMIFA_GBLCTL_NOHOLD_SHIFT 0x00000007u #define EMIFA_GBLCTL_NOHOLD_DEFAULT 0x00000000u #define EMIFA_GBLCTL_NOHOLD_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_NOHOLD_DISABLE 0x00000000u #define EMIFA_GBLCTL_NOHOLD_ENABLE 0x00000001u #define _EMIFA_GBLCTL_EK1HZ_MASK 0x00000040u #define _EMIFA_GBLCTL_EK1HZ_SHIFT 0x00000006u #define EMIFA_GBLCTL_EK1HZ_DEFAULT 0x00000001u #define EMIFA_GBLCTL_EK1HZ_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_EK1HZ_CLK 0x00000000u #define EMIFA_GBLCTL_EK1HZ_HIGHZ 0x00000001u #define _EMIFA_GBLCTL_EK1EN_MASK 0x00000020u #define _EMIFA_GBLCTL_EK1EN_SHIFT 0x00000005u #define EMIFA_GBLCTL_EK1EN_DEFAULT 0x00000001u #define EMIFA_GBLCTL_EK1EN_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_EK1EN_DISABLE 0x00000000u #define EMIFA_GBLCTL_EK1EN_ENABLE 0x00000001u #define _EMIFA_GBLCTL_CLK4EN_MASK 0x00000010u #define _EMIFA_GBLCTL_CLK4EN_SHIFT 0x00000004u #define EMIFA_GBLCTL_CLK4EN_DEFAULT 0x00000001u #define EMIFA_GBLCTL_CLK4EN_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_CLK4EN_DISABLE 0x00000000u #define EMIFA_GBLCTL_CLK4EN_ENABLE 0x00000001u #define _EMIFA_GBLCTL_CLK6EN_MASK 0x00000008u #define _EMIFA_GBLCTL_CLK6EN_SHIFT 0x00000003u #define EMIFA_GBLCTL_CLK6EN_DEFAULT 0x00000001u #define EMIFA_GBLCTL_CLK6EN_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_CLK6EN_DISABLE 0x00000000u #define EMIFA_GBLCTL_CLK6EN_ENABLE 0x00000001u #define EMIFA_GBLCTL_OF(x) _VALUEOF(x) #define EMIFA_GBLCTL_DEFAULT (Uint32)( \ 0x00000004\ |_PER_FDEFAULT(EMIFA,GBLCTL,EK2RATE)\ |_PER_FDEFAULT(EMIFA,GBLCTL,EK2HZ)\ |_PER_FDEFAULT(EMIFA,GBLCTL,EK2EN)\ |_PER_FDEFAULT(EMIFA,GBLCTL,BRMODE)\ |_PER_FDEFAULT(EMIFA,GBLCTL,BUSREQ)\ |_PER_FDEFAULT(EMIFA,GBLCTL,ARDY)\ |_PER_FDEFAULT(EMIFA,GBLCTL,HOLD)\ |_PER_FDEFAULT(EMIFA,GBLCTL,HOLDA)\ |_PER_FDEFAULT(EMIFA,GBLCTL,NOHOLD)\ |_PER_FDEFAULT(EMIFA,GBLCTL,EK1HZ)\ |_PER_FDEFAULT(EMIFA,GBLCTL,EK1EN)\ |_PER_FDEFAULT(EMIFA,GBLCTL,CLK4EN)\ |_PER_FDEFAULT(EMIFA,GBLCTL,CLK6EN)\ ) #define EMIFA_GBLCTL_RMK(ek2rate,ek2hz,ek2en,brmode,nohold,ek1hz,ek1en,clk4en,clk6en) \ (Uint32)( \ _PER_FMK(EMIFA,GBLCTL,EK2RATE,ek2rate)\ |_PER_FMK(EMIFA,GBLCTL,EK2HZ,ek2hz)\ |_PER_FMK(EMIFA,GBLCTL,EK2EN,ek2en)\ |_PER_FMK(EMIFA,GBLCTL,BRMODE,brmode)\ |_PER_FMK(EMIFA,GBLCTL,NOHOLD,nohold)\ |_PER_FMK(EMIFA,GBLCTL,EK1HZ,ek1hz)\ |_PER_FMK(EMIFA,GBLCTL,EK1EN,ek1en)\ |_PER_FMK(EMIFA,GBLCTL,CLK4EN,clk4en)\ |_PER_FMK(EMIFA,GBLCTL,CLK6EN,clk6en)\ ) #define _EMIFA_GBLCTL_FGET(FIELD)\ _PER_FGET(_EMIFA_GBLCTL_ADDR,EMIFA,GBLCTL,##FIELD) #define _EMIFA_GBLCTL_FSET(FIELD,field)\ _PER_FSET(_EMIFA_GBLCTL_ADDR,EMIFA,GBLCTL,##FIELD,field) #define _EMIFA_GBLCTL_FSETS(FIELD,SYM)\ _PER_FSETS(_EMIFA_GBLCTL_ADDR,EMIFA,GBLCTL,##FIELD,##SYM)/******************************************************************************\* _____________________* | |* | C E C T L |* |___________________|** CECTL0 - CE space control register 0* CECTL1 - CE space control register 1* CECTL2 - CE space control register 2* CECTL3 - CE space control register 3** FIELDS (msb -> lsb)* (rw) WRSETUP* (rw) WRSTRB* (rw) WRHLD* (rw) RDSETUP* (rw) TA* (rw) RDSTRB* (rw) MTYPE* (rw) RDHLD*\******************************************************************************/ #define _EMIFA_CECTL0_OFFSET 2 #define _EMIFA_CECTL1_OFFSET 1 #define _EMIFA_CECTL2_OFFSET 4 #define _EMIFA_CECTL3_OFFSET 5 #define _EMIFA_CECTL0_ADDR 0x01800008u #define _EMIFA_CECTL1_ADDR 0x01800004u #define _EMIFA_CECTL2_ADDR 0x01800010u #define _EMIFA_CECTL3_ADDR 0x01800014u #define _EMIFA_CECTL_WRSETUP_MASK 0xF0000000u #define _EMIFA_CECTL_WRSETUP_SHIFT 0x0000001Cu #define EMIFA_CECTL_WRSETUP_DEFAULT 0x0000000Fu #define EMIFA_CECTL_WRSETUP_OF(x) _VALUEOF(x) #define _EMIFA_CECTL_WRSTRB_MASK 0x0FC00000u #define _EMIFA_CECTL_WRSTRB_SHIFT 0x00000016u⌨️ 快捷键说明
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