booth_multiplier_stg.v

verilog程序

`define L_word 16
module Booth_Multiplier_STG(product,Ready,word1,word2,Start,clock,reset);
	output [2*`L_word-1:0]product;
	output Ready;
	input [`L_word-1:0]word1,word2;
	input Start,clock,reset;
	wire Load_words,Shift1,Shift2,Add,Sub,Ready;
	wire [2:0]BEC;
	
	Datapath m1(product,BEC,word1,word2,Load_words,Shift1,Shift2,Add,Sub,clock,reset);
	Controller m2(Load_words,Shift1,Shift2,Add,Sub,Ready,BEC,Start,clock,reset);
endmodule