rec_done.v

用FPGA实现任意波形发生器的源代码

module rec_done(clk,reset,rx,rx_ready,rx_hold);

input clk,rx,reset;
output rx_ready;
output [7:0]rx_hold;

reg rx_ready;
reg [7:0] rx_hold;

reg blk;
reg [1:0] state;
reg [4:0] count;
reg [2:0] data_count;

reg [7:0] cnt;

always@ ( posedge clk )
	begin
		if(cnt==64)
			begin
				cnt=0;
				blk=~blk;
				
			end
		else cnt=cnt+1;
	end			
	
	
	
always @( posedge blk )
	if ( !reset )
		begin
		rx_ready=0;
		rx_hold=0;
		state=0;
		count=0;
		data_count=0;
		
		end
	else	
			case ( state )			
				0:		begin
							if ( rx==0 )
								begin
								count=count+1;
								rx_ready=0;
								
								if ( count==8 )
									begin
									state=1;
									count=0;
					
									end
								end
							else
								count=0;	
						end
				1:				
									begin															
									count=count+1;								
									if ( count==16 )
										begin
										count=0;
										rx_hold[data_count]=rx;
										
											if ( data_count==7 )
												begin
												state=2;
												data_count=0;
												end
											else			
											data_count=data_count+1;	
										end		
									end												
				2:						
							if ( rx )
								begin
								 count=count+1;
								if ( count==16 )
									begin
										count=0;
										state=0;
										rx_ready=1;
									end
								end
							
				default:
					begin	
					state=0;					
					count=0;
					end
		endcase	
endmodule