sec.v

用FPGA实现任意波形发生器的源代码

module sec( clk,reset,tx_start,data,tx,tx_ready);
	input clk,tx_start,reset;
	input [7:0] data;
	output tx,tx_ready;
	
	
	
	reg tx,tx_ready;
	reg [3:0]count;
	reg [2:0]data_count;
	reg [1:0]state;
	reg tx_start_;  //the last state of tx_state;
	
//send
always @ ( posedge clk )
		if ( !reset )
			begin
			tx_start_=0;//tx_start;
			count=0;
			tx=1;
			state=0;
			data_count=0;
			tx_ready=1;
			end
		else
			case ( state ) 
				0:	
					if ( tx_start_ ^ tx_start & tx_start ) 
						begin
						state=1;
						tx_ready=0;
						end
					else
						tx_start_=tx_start;
					
				1:
					begin
						tx=0;
						count=count+1;
						if ( count==0 )
							state=2;
					end
				2:
					begin
						tx=data[data_count];
						count=count+1;
						if ( count==0 )
							begin
							data_count=data_count+1;
							if ( data_count==0 )
								state=3;
							end
					end
				3:
					begin
						tx=1;
						count=count+1;
						if ( count==0 )
							begin
							state=0;
							tx_ready=1;
						//	i=i+1;
							end
					end
			endcase
			
endmodule