📄 lan91c111.h
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// Interrupt Mask Register
/////////////
#define IM_REG MSMC | 0x000D
#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
#define IM_ERCV_INT 0x40 // Early Receive Interrupt
#define IM_EPH_INT 0x20 // Set by Etheret Protocol Handler section
#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
#define IM_TX_INT 0x02 // Transmit Interrrupt
#define IM_RCV_INT 0x01 // Receive Interrupt
#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_MDINT)
/////////////
// BANK 3 //
/////////////
// Multicast Table Registers
/////////////
#define MCAST_REG1 MSMC | 0x0000
#define MCAST_REG2 MSMC | 0x0002
#define MCAST_REG3 MSMC | 0x0004
#define MCAST_REG4 MSMC | 0x0006
/////////////
// BANK 3 //
/////////////
// Management Interface Register (MII)
/////////////
#define MII_REG MSMC | 0x0008
#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
#define MII_MDOE 0x0008 // MII Output Enable
#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
#define MII_MDI 0x0002 // MII Input, pin MDI
#define MII_MDO 0x0001 // MII Output, pin MDO
/////////////
// BANK 3 //
/////////////
// Revision Register
/////////////
#define REV_REG MSMC | 0x000A /* ( hi: chip id low: rev # ) */
/////////////
// BANK 3 //
/////////////
// Early RCV Register
/////////////
#define ERCV_REG MSMC | 0x000C
#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
///////////////////////////////////////
// PHY Register and bit definitions //
///////////////////////////////////////
// PHY Control Register
#define PHY_CNTL_REG 0x00
#define PHY_CNTL_RST 0x8000 // 1=PHY Reset
#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
// PHY Status Register
#define PHY_STAT_REG 0x01
#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
#define PHY_STAT_LINK 0x0004 // 1=valid link
#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
// PHY Identifier Registers
#define PHY_ID1_REG 0x02 // PHY Identifier 1
#define PHY_ID2_REG 0x03 // PHY Identifier 2
// PHY Auto-Negotiation Advertisement Register
#define PHY_AD_REG 0x04
#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
#define PHY_AD_ACK 0x4000 // 1=got link code word from remote
#define PHY_AD_RF 0x2000 // 1=advertise remote fault
#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
// PHY Auto-negotiation Remote End Capability Register
#define PHY_RMT_REG 0x05
// Uses same bit definitions as PHY_AD_REG
// PHY Configuration Register 1
#define PHY_CFG1_REG 0x10
#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
#define PHY_CFG1_TLVL_MASK 0x003C
#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
// PHY Configuration Register 2
#define PHY_CFG2_REG 0x11
#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
// PHY Status Output (and Interrupt status) Register
#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
#define PHY_INT_JAB 0x0100 // 1=Jabber detected
#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
// PHY Interrupt/Status Mask Register
#define PHY_MASK_REG 0x13 // Interrupt Mask
// Transmit status bits
#define TS_SUCCESS 0x0001
#define TS_LOSTCAR 0x0400
#define TS_LATCOL 0x0200
#define TS_16COL 0x0010
// Receive status bits
#define RS_ALGNERR 0x8000
#define RS_BRODCAST 0x4000
#define RS_BADCRC 0x2000
#define RS_ODDFRAME 0x1000 // bug: the LAN91C111 never sets this on receive
#define RS_TOOLONG 0x0800
#define RS_TOOSHORT 0x0400
#define RS_MULTICAST 0x0001
#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
////////////////////////////
// LAN Controller Structure
struct ADI_TOOLS_CLAN91C111_SMC_LOCAL_t {
// This keeps track of how many packets that I have
// sent out. When an TX_EMPTY interrupt comes, I know
// that all of these have been sent.
unsigned short packets_waiting;
// Last contents of PHY Register 18
unsigned short lastPhy18;
// Contains the current active transmission mode
unsigned short tcr_cur_mode;
// Contains the current active receive mode
unsigned short rcr_cur_mode;
// Contains the current active receive/phy mode
unsigned short rpc_cur_mode;
// Memory allocation for TX flag
unsigned short alloc_success;
////////////////
// DEBUG SECTION
// Contains the last packet size in receive
unsigned short rpsize;
// Set to true during the auto-negotiation sequence
unsigned char autoneg_active;
// Debug of the IRQ Service
unsigned char last_IRQ_serviced;
};
#define CS8900_BASE 0x20300000
typedef struct _ADI_ETHER_LAN91C111_DATA
{
ADI_ETHER_BUFFER *m_RxEnqueuedHead; // Head of RX buffers accepted for receiving incoming frames
ADI_ETHER_BUFFER *m_RxEnqueuedTail; // Tail of RX buffers accepted for receiving incoming frames
ADI_ETHER_BUFFER *m_RxDequeuedHead; // Head of RX buffers containing received incoming frames
ADI_ETHER_BUFFER *m_RxDequeuedTail; // Tail of RX buffers containing received incoming frames
ADI_ETHER_BUFFER *m_TxEnqueuedHead; // Head of TX buffers accepted for transmitting outgoing frames
ADI_ETHER_BUFFER *m_TxEnqueuedTail; // Tail of TX buffers accepted for transmitting outgoing frames
ADI_ETHER_BUFFER *m_TxDequeuedHead; // Head of TX buffers containing transmitted outgoing frames
ADI_ETHER_BUFFER *m_TxDequeuedTail; // Tail of TX buffers containing transmitted outgoing frames
int m_RxEnqueuedCount; // keeps track of the number of free receive bufs
int m_RxDequeuedCount; // keeps track of the number of full receive bufs
int m_TxEnqueuedCount; // keeps track of the number of full transmit bufs
int m_TxDequeuedCount; // keeps track of the number of free transmit bufs
struct ADI_TOOLS_CLAN91C111_SMC_LOCAL_t LAN_state;
char phyAddr[6];
int pf;// its the hex value with the pf pin bit set. if pf9 ->0x0200
long base_addr;//add LQL
long send_cmd;
int send_underrun;
interrupt_kind RXIVG;// rx ivg level
interrupt_kind TXIVG;// tx ivg level
interrupt_kind ERRIVG;// err ivg level
void *CriticalData;
ADI_DEV_DEVICE_HANDLE DeviceHandle; // device handle
ADI_DMA_MANAGER_HANDLE DMAHandle; // handle to the DMA manager
ADI_DCB_HANDLE DCBHandle; // callback handle
ADI_DCB_CALLBACK_FN DMCallback; // client callback function
ADI_DEV_DIRECTION Direction; // data direction
bool Open; // device open
bool Started; // device started
bool Closing; // refuse new requests
bool FlowEnabled; // data flow has been enabled
bool RxStarted; // set when at least one read issued
bool Loopback; // set the phy into loopback
bool Auto; // set auto negotiate
bool Port100; // 100 mbits
bool Cache; // Buffers may be cached
bool FullDuplex; // full duplex
ADI_ETHER_STATISTICS_COUNTS *Stats;
}ADI_ETHER_LAN91C111_DATA;
#endif /* __LAN91C111_H_ */
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