lan91c111.h

CS8900测试文件（整个工程） 环境：VDSP4.0

/*********************************************************************************

Copyright(c) 2004 Analog Devices, Inc. All Rights Reserved. 

This software is proprietary and confidential.  By using this software you agree
to the terms of the associated Analog Devices License Agreement.  



*********************************************************************************/
#ifndef __LAN91C111_H_
#define __LAN91C111_H_
#include <sys/exception.h>
#include <services/services.h>
#include <drivers/adi_dev.h>
#include <services/adi_dcb.h>
#include <services/adi_dma.h>
#include <services/adi_int.h>
#include <lwip/ADI_ETHER.h>


/////////////////////////////////////////////////////////////////////////////
// IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
// and FCS/CRC (frame check sequence).
/////////////////////////////////////////////////////////////////////////////
#define ETH_ALEN        6               /* Octets in one ethernet addr   */
#define ETH_HLEN        14              /* Total octets in header.       */
#define ETH_ZLEN        60              /* Min. octets in frame sans FCS */
#define ETH_DATA_LEN    1500            /* Max. octets in payload        */
#define ETH_FRAME_LEN   1514            /* Max. octets in frame sans FCS */

///////////////////////////////////////
// MAC Register and bit definitions  //
///////////////////////////////////////
/////////////
// BANK 0  //
/////////////
// Transmit Control Register
/////////////
#define TCR_REG         MSMC | 0x0000  // transmit control register
#define TCR_TXENA       0x0001  // When 1 we can transmit
#define TCR_LOOP        0x0002  // Controls output pin LBK
#define TCR_FORCOL      0x0004  // When 1 will force a collision
#define TCR_PAD_EN      0x0080  // When 1 will pad tx frames < 64 bytes w/0
#define TCR_NOCRC       0x0100  // When 1 will not append CRC to tx frames
#define TCR_MON_CSN     0x0400  // When 1 tx monitors carrier
#define TCR_FDUPLX      0x0800  // When 1 enables full duplex operation
#define TCR_STP_SQET    0x1000  // When 1 stops tx if Signal Quality Error
#define TCR_EPH_LOOP    0x2000  // When 1 enables EPH block loopback
#define TCR_SWFDUP      0x8000  // When 1 enables Switched Full Duplex mode
#define TCR_DEFAULT     TCR_TXENA | TCR_PAD_EN

/////////////
// BANK 0  //
/////////////
// EPH Status Register
/////////////
#define EPH_REG         MSMC | 0x0002
#define EPH_TX_SUC      0x0001  // Last TX was successful
#define EPH_SNGLCOL     0x0002  // Single collision detected for last tx
#define EPH_MULCOL      0x0004  // Multiple collisions detected for last tx
#define EPH_LTXMULT     0x0008  // Last tx was a multicast
#define EPH_16COL       0x0010  // 16 Collisions Reached
#define EPH_SQET        0x0020  // Signal Quality Error Test
#define EPH_LTXBRD      0x0040  // Last tx was a broadcast
#define EPH_TXDEFR      0x0080  // Transmit Deferred
#define EPH_LATCOL      0x0200  // Late collision detected on last tx
#define EPH_LOSTCARR    0x0400  // Lost Carrier Sense
#define EPH_EXC_DEF     0x0800  // Excessive Deferral
#define EPH_CTR_ROL     0x1000  // Counter Roll Over indication
#define EPH_LINK_OK     0x4000  // Driven by inverted value of nLNK pin
#define EPH_TXUNRN      0x8000  // Tx Underrun

/////////////
// BANK 0  //
/////////////
// Receive Control Register
/////////////
#define RCR_REG         MSMC | 0x0004
#define RCR_RX_ABORT    0x0001  // Set if a rx frame was aborted
#define RCR_PRMS        0x0002  // Enable promiscuous mode
#define RCR_ALMUL       0x0004  // When set accepts all multicast frames
#define RCR_RXEN        0x0100  // IFF this is set, we can receive packets
#define RCR_STRIPCRC    0x0200  // When set strips CRC from rx packets
#define RCR_ABORT_ENB   0x0200  // When set will abort rx on collision
#define RCR_FILTCAR     0x0400  // When set filters leading 12 bit s of carrier
#define RCR_SOFTRST     0x8000  // resets the chip
/* the normal settings for the RCR register : */
#define RCR_DEFAULT     (RCR_STRIPCRC | RCR_RXEN)
#define RCR_CLEAR       0x0     // set it to a base state

/////////////
// BANK 0  //
/////////////
// Counter Register
/////////////
#define COUNTER_REG     MSMC | 0x0006

/////////////
// BANK 0  //
/////////////
// Memory Information Register
/////////////
#define MIR_REG         MSMC | 0x0008

/////////////
// BANK 0  //
/////////////
// Receive/Phy Control Register
/////////////
#define RPC_REG         MSMC | 0x000A
#define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
#define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
#define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
#define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
#define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
#define RPC_LED_100_10  (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
#define RPC_LED_RES     (0x01)  // LED = Reserved
#define RPC_LED_10      (0x02)  // LED = 10Mbps link detect
#define RPC_LED_FD      (0x03)  // LED = Full Duplex Mode
#define RPC_LED_TX_RX   (0x04)  // LED = TX or RX packet occurred
#define RPC_LED_100     (0x05)  // LED = 100Mbps link dectect
#define RPC_LED_TX      (0x06)  // LED = TX packet occurred
#define RPC_LED_RX      (0x07)  // LED = RX packet occurred
/* the normal settings for the RCR register : */
#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100_10 << RPC_LSXA_SHFT) | (RPC_LED_TX_RX << RPC_LSXB_SHFT))

///////////////////
// BANK 0,1,2,3  //
///////////////////
// Bank Select Register
///////////////////
#define BSR_REG         MSMC | 0x000E

/////////////
// BANK 1  //
/////////////
// Configuration Reg
/////////////
#define CFG_REG         MSMC | 0x0000
#define CFG_EXTPHY      0x0200  // 1=external MII, 0=internal Phy
#define CFG_GPCNTRL     0x0400  // Inverse value drives pin nCNTRL
#define CFG_NOWAIT      0x1000  // When 1 no extra wait states on ISA bus
#define CFG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
#define CFG_RESERVED    0x20b1  // bit mask with "1"

/////////////
// BANK 1  //
/////////////
// Base Address Register
/////////////
#define BASE_REG        MSMC | 0x0002
#define BASE_DEFAULT    0x1801  // bit mask with "1"

/////////////
// BANK 1  //
/////////////
// Individual Address Registers
/////////////
#define ADDR0_REG       MSMC | 0x0004
#define ADDR1_REG       MSMC | 0x0006
#define ADDR2_REG       MSMC | 0x0008

/////////////
// BANK 1  //
/////////////
// General Purpose Register
/////////////
#define GP_REG          MSMC | 0x000A

/////////////
// BANK 1  //
/////////////
// Control Register
/////////////
#define CTL_REG         MSMC | 0x000C
#define CTL_RCV_BAD     0x4000 // When 1 bad CRC packets are received
#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
#define CTL_LEENABLE    0x0080 // When 1 enables Link Error interrupt
#define CTL_CRENABLE    0x0040 // When 1 enables Counter Rollover interrupt
#define CTL_TEENABLE    0x0020 // When 1 enables Transmit Error interrupt
#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
#define CTL_RELOAD      0x0002 // When set reads EEPROM into registers
#define CTL_STORE       0x0001 // When set stores registers into EEPROM

/////////////
// BANK 2  //
/////////////
// MMU Command Register
/////////////
#define MMU_CMD_REG     MSMC | 0x0000
#define MC_BUSY         1       // When 1 the last release has not completed
#define MC_NOP          (0<<5)  // No Op
#define MC_ALLOC        (1<<5)  // OR with number of 256 byte packets
#define MC_RESET        (2<<5)  // Reset MMU to initial state
#define MC_REMOVE       (3<<5)  // Remove the current rx packet
#define MC_RELEASE      (4<<5)  // Remove and release the current rx packet
#define MC_FREEPKT      (5<<5)  // Release packet in PNR register
#define MC_ENQUEUE      (6<<5)  // Enqueue the packet for transmit
#define MC_RSTTXFIFO    (7<<5)  // Reset the TX FIFOs

/////////////
// BANK 2  //
/////////////
// Packet Number Register
/////////////
#define PN_REG          MSMC | 0x0002

/////////////
// BANK 2  //
/////////////
// Allocation Result Register
/////////////
#define AR_REG          MSMC | 0x0003
#define AR_FAILED       0x80    // Alocation Failed

/////////////
// BANK 2  //
/////////////
// FIFO Ports Register
/////////////
#define FIFO_REG        MSMC | 0x0004  // Must be read as a word
#define RXFIFO_REMPTY   0x8000  // RX FIFO Empty
#define TXFIFO_TEMPTY   0x0080  // TX FIFO Empty

/////////////
// BANK 2  //
/////////////
// Pointer Register
/////////////
#define PTR_REG         MSMC | 0x0006
#define PTR_RCV         0x8000 // 1=Receive area, 0=Transmit area
#define PTR_AUTOINC     0x4000 // Auto increment the pointer on each access
#define PTR_READ        0x2000 // When 1 the operation is a read

/////////////
// BANK 2  //
/////////////
// Data Register 16bits or 32bits wide
/////////////
#define DATA_REG        MSMC | 0x0008

/////////////
// BANK 2  //
/////////////
// Interrupt Status/Acknowledge Register
/////////////
#define INT_REG         MSMC | 0x000C

/////////////
// BANK 2  //
/////////////