cs8900a_test.c

CS8900测试文件（整个工程） 环境：VDSP4.0

#include "cs8900a.h"
#include "lan91c111.h"
#include <cdefBF533.h>
#include <ccblkfn.h>

#define  net_device _ADI_ETHER_LAN91C111_DATA
#include <cplbtab.h> 

#define BASE 0x20300000

inline short inw(addr) {
	short ret;
	//asm("p0 = r0;");
	//asm("prefetch [p0]");
	//asm("prefetch [p0];");
	ret = *(short *)addr;
	
	return ret;	
}

inline void outw(x,addr){
	
	short * pAddr;
	pAddr = (short *)addr;
	
	*pAddr = x;	
/*	asm("prefetch [p1++];");
	asm("prefetch [p1++];");
	asm("prefetch [p1++];");
	asm("prefetch [p1++];");
	asm("prefetch [p1++];");
	asm("prefetch [p1++];");
	asm("prefetch [p1++];");
*/	
}

inline int readreg(struct net_device *dev, int portno) {
	short ret;
	outw(portno, dev->base_addr + ADD_PORT);
	ret = inw(dev->base_addr + DATA_PORT);
	return ret;
}

inline void writereg(struct net_device *dev, int portno, short value) {
	outw(portno, dev->base_addr + ADD_PORT);
	outw(value, dev->base_addr + DATA_PORT);
}

inline int readword(struct net_device *dev, int portno) {
	return inw(dev->base_addr + portno);
}

inline void writeword(struct net_device *dev, int portno, int value) {
	outw(value, dev->base_addr + portno);
}

inline void writeblock(struct net_device *dev, char *pData, int Length) {
    int i;

    for (i = 0 ; i < (Length/2); i++) {
        writeword(dev, TX_FRAME_PORT, *(u16 *)pData );
        pData += 2;
    }

    if (Length % 2) {
        u16 OddWordValue = *pData;
        writeword(dev, TX_FRAME_PORT, OddWordValue);
    }
}

inline void readblock(struct net_device *dev, char *pData, int Length) {
    u16 InputWord;
    int i;

    for (i=0; i < (Length/2); i++) {
        InputWord = readword(dev, RX_FRAME_PORT);
        *(u8*)pData++ = (u8) InputWord & 0xFF;
        *(u8*)pData++ = (u8) (InputWord >> 8) & 0xFF;
    }

    if (Length & 0x1)
      *pData = (u8) (readword(dev, RX_FRAME_PORT) & 0xff);
}
void cs8900a_probe(struct net_device *dev)
{
	//read ID	
	int rev_type,i, chip_type,chip_revision;
	
	rev_type = readreg(dev, PRODUCT_ID_ADD);	
	chip_type = rev_type&~REVISON_BITS;
	chip_revision = ((rev_type & REVISON_BITS) >> 8) + 'A';
	
	printf("Found CS89%c0 rev %c chipset.\n",chip_type == CS8900?'0':'2',chip_revision);
	//reset chip	
	writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET);
	//readreg(dev, PP_SelfCTL);
	
	//wait 30 ms 
	for(i=0;i<1000000;i++){
		i++;
	}
	//wait until reset done
	while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0){
		i++;
	}
	
	//reset for get mac!
	
	
	
}

int net_open(struct net_device *dev)
{
	//readreg(dev, PP_BusCTL);
	writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ);
	
	//writereg(dev, PP_BusCTL, 0xffff);
	//readreg(dev, PP_BusCTL);
	//disable irq
	//readreg(dev, PP_CS8900_ISAINT);
	writereg(dev, PP_CS8900_ISAINT, 0);//IRQ 0 
	//readreg(dev, PP_CS8900_ISAINT);
	
	
	 writereg(dev, PP_BusCTL, MEMORY_ON);	//使能MEMORY模式

    /* Set the LineCTL quintuplet */
  

    /* Turn on both receive and transmit operations */
    writereg(dev, PP_LineCTL,
	     readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON);//使能TX/RX

    /* Receive only error free packets addressed to this card */
   
    writereg(dev, PP_RxCTL, DEF_RX_ACCEPT);
   
    writereg(dev, PP_RxCFG,RX_OK_ENBL | RX_CRC_ERROR_ENBL );

    writereg(dev, PP_TxCFG,
	     TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL |
	     TX_LATE_COL_ENBL | TX_JBR_ENBL |
	     TX_ANY_COL_ENBL | TX_16_COL_ENBL);
	     
    writereg(dev, PP_BufCFG,
	     READY_FOR_TX_ENBL | RX_MISS_COUNT_OVRFLOW_ENBL |
	     TX_COL_COUNT_OVRFLOW_ENBL | TX_UNDERRUN_ENBL);	     
	
	writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) | ENABLE_IRQ);
	/* move to here */	
	
	/*
	ret = request_irq(dev->irq, &net_interrupt, SA_INTERRUPT, "cs89x0", dev);	
    	if (ret)
	{
 		printk("%s: request_irq(%d) failed\n", dev->name, dev->irq);
		goto bad_out;
  	}
  		
    enable_irq(dev->irq);
    */
}

int net_close(struct net_device *dev)
{

	writereg(dev, PP_RxCFG, 0);
	writereg(dev, PP_TxCFG, 0);
	writereg(dev, PP_BufCFG, 0);
	writereg(dev, PP_BusCTL, 0);

	/* Update the statistics here. */
	return 0;
}
#if 0
int net_send_packet(struct sk_buff *skb, struct net_device *dev)
{
    struct net_local *lp = (struct net_local *)dev->priv;

    writereg(dev, PP_BusCTL, 0x0);
    writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) | ENABLE_IRQ);

    DPRINTK(3, "%s: sent %d byte packet of type %x\n",
	    dev->name, skb->len,
	    (skb->data[ETH_ALEN+ETH_ALEN] << 8) |
	    (skb->data[ETH_ALEN+ETH_ALEN+1]));

    /* keep the upload from being interrupted, since we
       ask the chip to start transmitting before the
       whole packet has been completely uploaded. */

    spin_lock_irq(&lp->lock);
    netif_stop_queue(dev);

    /* initiate a transmit sequence */
    writeword(dev, TX_CMD_PORT, lp->send_cmd);
    writeword(dev, TX_LEN_PORT, skb->len);

    /* Test to see if the chip has allocated memory for the packet */
    if ((readreg(dev, PP_BusST) & READY_FOR_TX_NOW) == 0) {
      /*
       * Gasp!  It hasn't.  But that shouldn't happen since
       * we're waiting for TxOk, so return 1 and requeue this packet.
       */
		
      spin_unlock_irq(&lp->lock);
      DPRINTK(1, "cs89x0: Tx buffer not free!\n");
      return 1;
    }
    /* Write the contents of the packet */
    writeblock(dev, skb->data, skb->len);

    spin_unlock_irq(&lp->lock);
    dev->trans_start = jiffies;
    dev_kfree_skb (skb);

    /*
     * We DO NOT call netif_wake_queue() here.
     * We also DO NOT call netif_start_queue().
     *
     * Either of these would cause another bottom half run through
     * net_send_packet() before this packet has fully gone out.  That causes
     * us to hit the "Gasp!" above and the send is rescheduled.  it runs like
     * a dog.  We just return and wait for the Tx completion interrupt handler
     * to restart the netdevice layer
     */

    return 0;
}
#endif

void main()
{

	*pEBIU_AMBCTL0 = 0x78B078B0;
	*pEBIU_AMBCTL1 = 0x78B078B0;
	*pEBIU_AMGCTL |= 0xF;
	ssync();
	struct net_device dev;
	
	dev.base_addr = BASE;
//	dev.irq=27;
	
	int rev_type[10],i;
	for(i=0;i<10;i++)
	{
	rev_type[i] = readreg(&dev, 0x0);
	}
/*	
	while(1)
	{
	}
*/	
	cs8900a_probe(&dev);
		
	
	net_open(&dev);
	
	while(1)
	{
	}
	return;
}