i82801smbpep.h

此文件是cp6000主板的bsp包

/* i82801SmbPep.h - Header for the Intel 82801 SMBus library */

/* Copyright 2004 Kontron Modular Computers GmbH */

/*
modification history
--------------------
01e,10feb02,gko added support for Hance Rapids ICH
01d,01aug02,phd copyright adjusted
                added support (new device id) for ICH4 
01c,25feb02,tsi	added support (new device id) for CICH 
01b,12oct01,sbi	defines for power management added
01a,29sep01,mgr	created ( adapted from i82371SmbPep.h )
*/

#ifndef __INCi82801SmbPep_h
#define __INCi82801SmbPep_h

#ifdef __cplusplus
extern "C" {
#endif

/* includes */

#include "versionPep.h"
#include "drv/i2c/smbPep.h"

/* defines */

PEP_VERSION(i82801SmbPep_h,01e)				/* version identifier */

#define I82801_VENDOR_ID		0x8086		/* PCI vendor ID */
#define I82801BA_SMB_DEVICE_ID	0x2443		/* PCI device ID for SMB host (ICH2) */
#define I82801BA_LPC_DEVICE_ID	0x2440		/* PCI device ID for LPC bridge (ICH2) */
#define I82801DB_SMB_DEVICE_ID	0x24c3		/* PCI device ID for SMB host (ICH4) */
#define I82801DB_LPC_DEVICE_ID	0x24c0		/* PCI device ID for LPC bridge (ICH4) */
#define I82801E_SMB_DEVICE_ID	0x2453		/* PCI device ID for SMB host (CICH) */
#define I82801E_LPC_DEVICE_ID	0x2450		/* PCI device ID for LPC bridge (CICH) */
#define I82801HR_SMB_DEVICE_ID  0x25A4	    /* PCI device ID for SMB host (6300ESB=Hance Rapids) */
#define I82801HR_LPC_DEVICE_ID  0x25A1	    /* PCI device ID for LPC bridge (6300ESB=Hance Rapids) */
#define I82801_SMB_DEVICE_NO	0			/* used instance of the SMB host */
#define I82801_LPC_DEVICE_NO	0			/* used instance of the LPC bridge */
#define I82801_SMB_IRQ_NUM		9			/* default interrupt number */
#define I82801_SMB_ARA			0x0c		/* SMBus alert response address */

/* register offset definitions */

/* PCI configuration register offsets */
#define I82801_REG_COMMAND			0x04	/* PCI command regiser */
#define	I82801_REG_INTLN			0x3c	/* PCI interrupt line */
#define I82801_REG_PMBA				0x40	/* power management base address */
#define I82801_REG_SMBBA			0x20	/* SMBus base address  */
#define I82801_REG_SMBHSTCFG		0x40	/* SMBus host configuration */

/* power management IO space register offsets */
#define I82801_REG_PMCNTRL	   		0x04	/* power management control register */
#define I82801_REG_GPSTS	   		0x28	/* general purpose status register */
#define I82801_REG_GPEN		   		0x2A	/* general purpose enable register */
#define I82801_REG_GLBCTL	   		0x2A	/* global control register */

/* SMBus IO space register offsets */
#define I82801_REG_SMBHSTSTS		0x00	/* SMBus host status register */
#define I82801_REG_SMBSLVSTS		0x01	/* SMBus slave status register */
#define I82801_REG_SMBHSTCNT		0x02	/* SMBus host control regsiter */
#define I82801_REG_SMBHSTCMD		0x03	/* SMBus host command register */
#define I82801_REG_SMBHSTADD		0x04	/* SMBus Transmit Slave Address */
#define I82801_REG_SMBHSTDAT0		0x05	/* SMBus host data 0 register */
#define I82801_REG_SMBHSTDAT1		0x06	/* SMBus host data 1 register */
#define I82801_REG_SMBBLKDAT		0x07	/* SMBus block data register */
#define I82801_REG_SMBRCVSLV		0x09	/* SMBus Receive Slave Address  */
#define I82801_REG_SMBSLVCMD		0x11	/* SMBus slave command register */
#define I82801_REG_SMBSLVDAT		0x0A	/* SMBus slave data register */

#define I82801_REG_SMBSMLINKPINCTL	0x0E	/* SMBus smlink pin control */
#define I82801_REG_SMBSMBUSPINCTL	0x0F	/* SMBus SMBus Pin Control */

/* register bit definitions */

/* PCI configuration header */
#define I82801_COMMAND_IOSC			(1<<0)	/* I/O space control */

/* SMBHSTSTS */
#define I82801_SMBHSTSTS_DONE			(1<<7)	/* Done status for Block Read/Write Byte transfers */
#define I82801_SMBHSTSTS_INUSE			(1<<6)	/* bit used as semaphore for access on I2C bus */
#define I82801_SMBHSTSTS_ALERT			(1<<5)	/* SMBus alert status */
#define I82801_SMBHSTSTS_FAILED		(1<<4)	/* transfer failed */
#define I82801_SMBHSTSTS_BUS_ERR		(1<<3)	/* bus transfer collision */
#define I82801_SMBHSTSTS_DEV_ERR		(1<<2)	/* device error */
#define I82801_SMBHSTSTS_INTER			(1<<1)	/* transfer finished */
#define I82801_SMBHSTSTS_HOST_BUSY	(1<<0)	/* host busy */

/* SMBHSTCNT */
#define I82801_SMBHSTCNT_QRW		0		/* quick read/write */		/* xxx0 00xx */
#define I82801_SMBHSTCNT_BRW		(1<<2)	/* byte read/write */ 		/* xxx0 01xx */
#define I82801_SMBHSTCNT_BDRW		(2<<2)	/* byte data read/write */	/* xxx0 10xx */
#define I82801_SMBHSTCNT_WDRW		(3<<2)	/* word data read/write */	/* xxx0 11xx */
#define I82801_SMBHSTCNT_PROC		(4<<2)	/* process call */			/* xxx1 00xx */
#define I82801_SMBHSTCNT_BLRW		(5<<2)	/* block read/write */		/* xxx1 01xx */
#define I82801_SMBHSTCNT_I2C		(6<<2)	/* I2C read */				/* xxx1 10xx */

#define I82801_SMBHSTCNT_START		(1<<6)	/* start transfer */
#define I82801_SMBHSTCNT_KILL		(1<<1)	/* abort transfer */
#define I82801_SMBHSTCNT_INTEREN	(1<<0)	/* enable IRQ9 */

/* SMBHSTADD */
#define I82801_SMBHSTADD_RW			(1<<0)	/* read/write address bit */

/* SMBHSTCFG */
#define I82801_SMBHSTCFG_ENABLE		(1<<0)	/* enable SMBus controller */

/*  SMBSLVCMD */
#define I82801_SMBSLVCMD_SMBALERT_DISABLE	(1<<2)	/* disable the generation of the interrupt*/

/* PWM IO space registers bit definitions */

/* PMCNTRL */
#define I82801_PWMPMCNTRL_SCI_EN	(1<<0)	/* enable SCI generation */

/* GPSTS */
#define I82801_PWMGPSTS_THRM_STS	(1<<0)	/* thermal status */

/* GPEN */
#define I82801_PWMGPEN_THRM_EN		(1<<0)	/* enable THRM */

/* GLBCTL */
#define I82801_PWMGLBCTL_THRM_POL	(1<<2)	/* active low asserts THRM */

/* function number of power management */
#define I82801_PCI_FUNC_NO_POW_MAN	0

/* function declarations */

#if defined(__STDC__) || defined(__cplusplus)

IMPORT SMB_FUNCS* i82801SmbInit ();

#else

IMPORT SMB_FUNCS* i82801SmbInit ();

#endif	/* __STDC__ */


#ifdef __cplusplus
}
#endif

#endif /* __INCI82801SmbPep_h */