i86hwdpep.h

此文件是cp6000主板的bsp包

/* i86HwdPep.h - header for the hardware watchdog library */

/* Copyright 2002 Kontron Modular Computers GmbH */

/*
modification history
--------------------
01a,23aug02,phd created
*/

#ifndef __INCi86HwdPep_h
#define __INCi86HwdPep_h

#ifdef __cplusplus
extern "C" {
#endif

/* includes */

#include "vxWorks.h"
#include "versionPep.h"

/* defines */

PEP_VERSION(i86HwdPep_h,01a)			/* version identifier */

/* watchdog I/O port definitions */

#define	HWDOG_TRIGGER_REG		0x280	/* watchdog trigger register */
#define	HWDOG_TIMEOUT_REG		0x282	/* timeout configuration register */
#define	HWDOG_IRQCFG_REG		0x284	/* interrupt configuration register */
#define	HWDOG_IOSTAT_REG		0x286	/* I/O status register */

/* watchdog control bit definitions */

#define	HWDOG_ENABLE			(1<<4)	/* enable the watchdog timer */
#define	HWDOG_RESET_DETECTED	(1<<5)	/* watchdog has generated a reset */

#define	HWDOG_IRQCFG_MASK		0x87	/* mask for interrupt routing bits */
#define	HWDOG_IRQCFG_SMI		(1<<0)	/* routes watchdog output to SMI */
#define	HWDOG_IRQCFG_IRQ5		(1<<1)	/* routes watchdog output to IRQ5 */
#define	HWDOG_IRQCFG_RESET		(1<<2)	/* routes watchdog output to RESET */
#define	HWDOG_IRQCFG_NMI		(1<<7)	/* routes watchdog output to NMI */
#define	HWDOG_IRQCFG_DUAL		(HWDOG_IRQCFG_RESET | HWDOG_IRQCFG_NMI)

#define	HWDOG_IOSTAT_WST		(1<<7)	/* watchdog timout has occured */

/* watchdog timeout definitions */

#define	HWDOG_TIMEOUT_125MS		0		/* 125 ms timeout period */
#define	HWDOG_TIMEOUT_250MS		1		/* 250 ms timeout period */
#define	HWDOG_TIMEOUT_500MS		2		/* 500 ms timeout period */
#define	HWDOG_TIMEOUT_1S		3		/*   1  s timeout period */
#define	HWDOG_TIMEOUT_2S		4		/*   2  s timeout period */
#define	HWDOG_TIMEOUT_4S		5		/*   4  s timeout period */
#define	HWDOG_TIMEOUT_8S		6		/*   8  s timeout period */
#define	HWDOG_TIMEOUT_16S		7		/*  16  s timeout period */
#define	HWDOG_TIMEOUT_32S		8		/*  32  s timeout period */
#define	HWDOG_TIMEOUT_64S		9		/*  64  s timeout period */
#define	HWDOG_TIMEOUT_128S		10		/* 128  s timeout period */
#define	HWDOG_TIMEOUT_256S		11		/* 256  s timeout period */

/* watchdog routing definitions */

#define	HWDOG_ROUTE_RESET		0		/* route watchdog output to RESET */
#define	HWDOG_ROUTE_IRQ5		1		/* route watchdog output to IRQ5 */
#define	HWDOG_ROUTE_SMI			2		/* route watchdog output to SMI */
#define	HWDOG_ROUTE_NMI			3		/* route watchdog output to NMI */
#define	HWDOG_ROUTE_DUAL		4		/* set watchdog to dual stage mode */

/* watchdog NMI definitions */

#define HWDOG_NMI_SC			0x61	/* NMI status control register */
#define HWDOG_IOCHK_NMI_STS		(1<<6)	/* IOCHK# NMI source status bit */
#define HWDOG_IOCHK_NMI_EN		(1<<3)	/* IOCHK# NMI enable bit */

/* function declarations */

#if defined(__STDC__) || defined(__cplusplus)

IMPORT STATUS hwdStart (int delay, int routing, VOIDFUNCPTR pIrqHook, int parameter);
IMPORT VOID hwdTrigger (VOID);
IMPORT BOOL hwdTimoutCheck (VOID);
IMPORT BOOL hwdNmiCheck (VOID);
IMPORT VOID	hwdNmiClear (VOID);
IMPORT BOOL hwdDualStageModeCheck (VOID);
IMPORT VOID hwdDualStageModeClear (VOID);
IMPORT VOID hwdDualStageModeSet (VOID);
IMPORT VOID hwdDemoIrqHandler (int parameter);

#else

IMPORT STATUS hwdStart ();
IMPORT VOID hwdTrigger ();
IMPORT BOOL hwdTimoutCheck ();
IMPORT BOOL hwdNmiCheck ();
IMPORT VOID	hwdNmiClear ();
IMPORT BOOL hwdDualStageModeCheck ();
IMPORT VOID hwdDualStageModeClear ();
IMPORT VOID hwdDualStageModeSet ();
IMPORT VOID hwdDemoIrqHandler ();

#endif	/* __STDC__ */

/* reference to drag in the component */

LOCAL FUNCPTR pHwdStart __attribute__ ((unused)) = hwdStart;

#ifdef __cplusplus
}
#endif

#endif /* __INCi86HwdPep_h */

/* eof */