fpga313czkz.tan.rpt

windowsxp/2000下驱动程序开发软件winddriver6.0

+-----------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                  ;
+-------------------------------------------------------+--------------------+------+---------+-------------+
; Option                                                ; Setting            ; From ; To      ; Entity Name ;
+-------------------------------------------------------+--------------------+------+---------+-------------+
; Device Name                                           ; EPF10K20TI144-4    ;      ;         ;             ;
; Timing Models                                         ; Final              ;      ;         ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;         ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;         ;             ;
; Number of paths to report                             ; 200                ;      ;         ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;         ;             ;
; Use Fast Timing Models                                ; Off                ;      ;         ;             ;
; Report IO Paths Separately                            ; Off                ;      ;         ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;         ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;         ;             ;
; Cut off read during write signal paths                ; On                 ;      ;         ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;         ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;         ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;         ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;         ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;         ;             ;
; Enable Clock Latency                                  ; Off                ;      ;         ;             ;
; Clock Settings                                        ; clk 1us            ;      ; clk_1us ;             ;
; Clock Settings                                        ; clk in             ;      ; clk_in  ;             ;
+-------------------------------------------------------+--------------------+------+---------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                    ;
+-----------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+----------+--------------+
; Clock Node Name ; Clock Setting Name ; Type          ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset   ; Phase offset ;
+-----------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+----------+--------------+
; clk_1us         ; clk_1us            ; Internal Node ; 1.0 MHz          ; 0.000 ns      ; 0.000 ns     ; clk_in   ; 1                     ; 40                  ; 6.400 ns ;              ;
; clk_in          ; clk_in             ; User Pin      ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A      ;              ;
+-----------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_1us'                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                    ; To                                ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 961.400 ns                              ; 25.91 MHz ( period = 38.600 ns )                    ; search_panel:m1|scan_reg8:scan2|q[0]    ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 35.000 ns               ;
; 961.400 ns                              ; 25.91 MHz ( period = 38.600 ns )                    ; search_panel:m1|scan_reg8:scan3|q[0]    ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 35.000 ns               ;
; 961.900 ns                              ; 26.25 MHz ( period = 38.100 ns )                    ; search_panel:m1|ttl_cnt[3]              ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 34.500 ns               ;
; 963.100 ns                              ; 27.10 MHz ( period = 36.900 ns )                    ; search_panel:m1|ttl_cnt[2]              ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 33.300 ns               ;
; 963.300 ns                              ; 27.25 MHz ( period = 36.700 ns )                    ; search_panel:m1|scan_reg8:scan2|q[5]    ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 33.100 ns               ;
; 963.600 ns                              ; 27.47 MHz ( period = 36.400 ns )                    ; search_panel:m1|ram_initionalize_cnt[0] ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 32.800 ns               ;
; 963.700 ns                              ; 27.55 MHz ( period = 36.300 ns )                    ; search_panel:m1|scan_reg8:scan0|q[5]    ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 32.700 ns               ;
; 963.700 ns                              ; 27.55 MHz ( period = 36.300 ns )                    ; search_panel:m1|ram_initionalize_cnt[3] ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 32.700 ns               ;
; 964.200 ns                              ; 27.93 MHz ( period = 35.800 ns )                    ; search_panel:m1|ttl_cnt[4]              ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 32.200 ns               ;
; 964.300 ns                              ; 28.01 MHz ( period = 35.700 ns )                    ; search_panel:m1|ttl_cnt[5]              ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 32.100 ns               ;
; 964.800 ns                              ; 28.41 MHz ( period = 35.200 ns )                    ; search_panel:m1|scan_reg8:scan3|q[4]    ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 31.600 ns               ;
; 965.600 ns                              ; 29.07 MHz ( period = 34.400 ns )                    ; search_panel:m1|ram_initionalize_cnt[2] ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 30.800 ns               ;
; 965.800 ns                              ; 29.24 MHz ( period = 34.200 ns )                    ; search_panel:m1|scan_reg8:scan3|q[6]    ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 30.600 ns               ;
; 965.900 ns                              ; 29.33 MHz ( period = 34.100 ns )                    ; search_panel:m1|scan_reg8:scan4|q[1]    ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 30.500 ns               ;
; 965.900 ns                              ; 29.33 MHz ( period = 34.100 ns )                    ; search_panel:m1|ram_initionalize_cnt[1] ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 30.500 ns               ;
; 966.100 ns                              ; 29.50 MHz ( period = 33.900 ns )                    ; search_panel:m1|scan_reg8:scan4|q[5]    ; search_panel:m1|key_reg           ; clk_1us    ; clk_1us  ; 1000.000 ns                 ; 996.400 ns                ; 30.300 ns               ;