📄 fpga313czkz.map.rpt
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Analysis & Synthesis report for fpga313czkz
Mon Jul 17 09:09:30 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis RAM Summary
8. State Machine - |fpga313czkz|parallel_port:m4|mach_rd_next
9. State Machine - |fpga313czkz|parallel_port:m4|mach_tr_next
10. State Machine - |fpga313czkz|main:m2|mach_next
11. State Machine - |fpga313czkz|search_panel:m1|mach_next
12. General Register Statistics
13. Parameter Settings for User Entity Instance: search_panel:m1
14. Parameter Settings for User Entity Instance: search_panel:m1|ttl128bit_dq:ttl_ram|lpm_ram_dq:lpm_ram_dq_component
15. Parameter Settings for User Entity Instance: main:m2
16. Parameter Settings for User Entity Instance: parallel_port:m4
17. Parameter Settings for Inferred Entity Instance: search_panel:m1|lpm_counter:scan_cnt_rtl_0
18. Parameter Settings for Inferred Entity Instance: parallel_port:m4|lpm_counter:delay_count0_rtl_1
19. Parameter Settings for Inferred Entity Instance: lpm_counter:cnt1_rtl_2
20. Parameter Settings for Inferred Entity Instance: parallel_port:m4|lpm_add_sub:add_rtl_3
21. Parameter Settings for Inferred Entity Instance: main:m2|lpm_add_sub:add_rtl_4
22. Parameter Settings for Inferred Entity Instance: search_panel:m1|lpm_add_sub:add_rtl_5
23. Parameter Settings for Inferred Entity Instance: search_panel:m1|lpm_add_sub:add_rtl_6
24. Parameter Settings for Inferred Entity Instance: search_panel:m1|lpm_add_sub:add_rtl_7
25. Analysis & Synthesis Equations
26. Analysis & Synthesis Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Jul 17 09:09:30 2006 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; fpga313czkz ;
; Top-level Entity Name ; fpga313czkz ;
; Family ; FLEX10K ;
; Total logic elements ; 863 ;
; Total pins ; 95 ;
; Total memory bits ; 128 ;
+-----------------------------+------------------------------------------+
+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------+-----------------+---------------+
; Device ; EPF10K20TI144-4 ; ;
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