fpga313czkz.hier_info

windowsxp/2000下驱动程序开发软件winddriver6.0

|fpga313czkz
clk_in => cnt1[14].CLK
clk_in => cnt1[13].CLK
clk_in => cnt1[12].CLK
clk_in => cnt1[11].CLK
clk_in => cnt1[10].CLK
clk_in => cnt1[9].CLK
clk_in => cnt1[8].CLK
clk_in => cnt1[7].CLK
clk_in => cnt1[6].CLK
clk_in => cnt1[5].CLK
clk_in => cnt1[4].CLK
clk_in => cnt1[3].CLK
clk_in => cnt1[2].CLK
clk_in => cnt1[1].CLK
clk_in => cnt1[0].CLK
clk_in => clk_1us.CLK
clk_in => cnt1[15].CLK
switchin[0] => switchin[0]~7.IN1
switchin[1] => switchin[1]~6.IN1
switchin[2] => switchin[2]~5.IN1
switchin[3] => switchin[3]~4.IN1
switchin[4] => switchin[4]~3.IN1
switchin[5] => switchin[5]~2.IN1
switchin[6] => switchin[6]~1.IN1
switchin[7] => switchin[7]~0.IN1
switchen[1] <= search_panel:m1.switch_se
switchen[2] <= search_panel:m1.switch_se
switchen[3] <= search_panel:m1.switch_se
switchen[4] <= search_panel:m1.switch_se
switchen[5] <= search_panel:m1.switch_se
switchen[6] <= search_panel:m1.switch_se
switchen[7] <= search_panel:m1.switch_se
switchen[8] <= search_panel:m1.switch_se
switchen[9] <= search_panel:m1.switch_se
lamptest => lamp_test.IN1
lampout[1] <= lamp:m3.lamp_out
lampout[2] <= lamp:m3.lamp_out
lampout[3] <= lamp:m3.lamp_out
lampout[4] <= lamp:m3.lamp_out
lampout[5] <= lamp:m3.lamp_out
lampout[6] <= lamp:m3.lamp_out
lampout[7] <= lamp:m3.lamp_out
lampout[8] <= lamp:m3.lamp_out
lampout[9] <= lamp:m3.lamp_out
lampout[10] <= lamp:m3.lamp_out
lampout[11] <= lamp:m3.lamp_out
lampout[12] <= lamp:m3.lamp_out
lampout[13] <= lamp:m3.lamp_out
lampout[14] <= lamp:m3.lamp_out
lampout[15] <= lamp:m3.lamp_out
lampout[16] <= lamp:m3.lamp_out
lampout[17] <= lamp:m3.lamp_out
lampout[18] <= lamp:m3.lamp_out
lampout[19] <= lamp:m3.lamp_out
lampout[20] <= lamp:m3.lamp_out
lampout[21] <= lamp:m3.lamp_out
lampout[22] <= lamp:m3.lamp_out
lampout[23] <= lamp:m3.lamp_out
lampout[24] <= lamp:m3.lamp_out
lampout[25] <= lamp:m3.lamp_out
lampout[26] <= lamp:m3.lamp_out
lampout[27] <= lamp:m3.lamp_out
lampout[28] <= lamp:m3.lamp_out
lampout[29] <= lamp:m3.lamp_out
lampout[30] <= lamp:m3.lamp_out
lampout[31] <= lamp:m3.lamp_out
lampout[32] <= lamp:m3.lamp_out
lampout[33] <= lamp:m3.lamp_out
lampout[34] <= lamp:m3.lamp_out
lampout[35] <= lamp:m3.lamp_out
lampout[36] <= lamp:m3.lamp_out
lampout[37] <= lamp:m3.lamp_out
lampout[38] <= lamp:m3.lamp_out
lampout[39] <= lamp:m3.lamp_out
lampout[40] <= lamp:m3.lamp_out
lampout[41] <= lamp:m3.lamp_out
lampout[42] <= lamp:m3.lamp_out
lampout[43] <= lamp:m3.lamp_out
lampout[44] <= lamp:m3.lamp_out
lampout[45] <= lamp:m3.lamp_out
lampout[46] <= lamp:m3.lamp_out
lampout[47] <= lamp:m3.lamp_out
lampout[48] <= lamp:m3.lamp_out
lampout[49] <= lamp:m3.lamp_out
lampout[50] <= lamp:m3.lamp_out
lampout[51] <= lamp:m3.lamp_out
lampout[52] <= lamp:m3.lamp_out
lampout[53] <= lamp:m3.lamp_out
lampout[54] <= lamp:m3.lamp_out
lampout[55] <= lamp:m3.lamp_out
lampout[56] <= lamp:m3.lamp_out
lampout[57] <= lamp:m3.lamp_out
lampout[58] <= lamp:m3.lamp_out
lampout[59] <= lamp:m3.lamp_out
lampout[60] <= lamp:m3.lamp_out
lampout[61] <= lamp:m3.lamp_out
lampout[62] <= lamp:m3.lamp_out
lampout[63] <= lamp:m3.lamp_out
lampout[64] <= lamp:m3.lamp_out
lampout[65] <= lamp:m3.lamp_out
paradata[0] <= paradata~7
paradata[0] <= parallel_port:m4.para_datain
paradata[1] <= paradata~6
paradata[1] <= parallel_port:m4.para_datain
paradata[2] <= paradata~5
paradata[2] <= parallel_port:m4.para_datain
paradata[3] <= paradata~4
paradata[3] <= parallel_port:m4.para_datain
paradata[4] <= paradata~3
paradata[4] <= parallel_port:m4.para_datain
paradata[5] <= paradata~2
paradata[5] <= parallel_port:m4.para_datain
paradata[6] <= paradata~1
paradata[6] <= parallel_port:m4.para_datain
paradata[7] <= paradata~0
paradata[7] <= parallel_port:m4.para_datain
para_dir <= parallel_port:m4.para_dir
selctin => selctin_inv.IN1
ackout <= parallel_port:m4.ackout


|fpga313czkz|search_panel:m1
clk => clk~0.IN9
clk_ram => clk_ram~0.IN1
reset_n => scan_cnt[2].ACLR
reset_n => ttl_we~3.OUTPUTSELECT
reset_n => key_reg~1.OUTPUTSELECT
reset_n => scan_cnt[1].ACLR
reset_n => scan_cnt[0].ACLR
reset_n => scan_cnt[3].ACLR
reset_n => ram_initadd[5].ACLR
reset_n => ram_initadd[4].ACLR
reset_n => ram_initadd[3].ACLR
reset_n => ram_initadd[2].ACLR
reset_n => ram_initadd[1].ACLR
reset_n => ram_initadd[0].ACLR
reset_n => ram_initadd[6].ACLR
reset_n => int_trig_en.ACLR
reset_n => ttl_cnt[6].ENA
reset_n => ttl_cnt[5].ENA
reset_n => ttl_cnt[4].ENA
reset_n => ttl_cnt[3].ENA
reset_n => ttl_cnt[2].ENA
reset_n => ttl_cnt[1].ENA
reset_n => ttl_cnt[0].ENA
reset_n => delay[31].ENA
reset_n => delay[30].ENA
reset_n => delay[29].ENA
reset_n => delay[28].ENA
reset_n => delay[27].ENA
reset_n => delay[26].ENA
reset_n => delay[25].ENA
reset_n => delay[24].ENA
reset_n => delay[23].ENA
reset_n => delay[22].ENA
reset_n => delay[21].ENA
reset_n => delay[20].ENA
reset_n => delay[19].ENA
reset_n => delay[18].ENA
reset_n => delay[17].ENA
reset_n => delay[16].ENA
reset_n => delay[15].ENA
reset_n => delay[14].ENA
reset_n => delay[13].ENA
reset_n => delay[12].ENA
reset_n => delay[11].ENA
reset_n => delay[10].ENA
reset_n => delay[9].ENA
reset_n => delay[8].ENA
reset_n => delay[7].ENA
reset_n => delay[6].ENA
reset_n => delay[5].ENA
reset_n => delay[4].ENA
reset_n => delay[3].ENA
reset_n => delay[2].ENA
reset_n => delay[1].ENA
reset_n => delay[0].ENA
reset_n => int_trig.ENA
reset_n => initionalize_flag.ENA
reset_n => ram_initionalize_cnt[6].ENA
reset_n => ram_initionalize_cnt[5].ENA
reset_n => ram_initionalize_cnt[4].ENA
reset_n => ram_initionalize_cnt[3].ENA
reset_n => ram_initionalize_cnt[2].ENA
reset_n => ram_initionalize_cnt[1].ENA
reset_n => ram_initionalize_cnt[0].ENA
reset_n => mach_next~7.IN1
sw_ack => sw_int~reg0.ACLR
switchin[0] => switchin[0]~7.IN9
switchin[1] => switchin[1]~6.IN9
switchin[2] => switchin[2]~5.IN9
switchin[3] => switchin[3]~4.IN9
switchin[4] => switchin[4]~3.IN9
switchin[5] => switchin[5]~2.IN9
switchin[6] => switchin[6]~1.IN9
switchin[7] => switchin[7]~0.IN9
sw_int <= sw_int~reg0.DB_MAX_OUTPUT_PORT_TYPE
keycode[0] <= sw_data_out[0].DB_MAX_OUTPUT_PORT_TYPE
keycode[1] <= sw_data_out[1].DB_MAX_OUTPUT_PORT_TYPE
keycode[2] <= sw_data_out[2].DB_MAX_OUTPUT_PORT_TYPE
keycode[3] <= sw_data_out[3].DB_MAX_OUTPUT_PORT_TYPE
keycode[4] <= sw_data_out[4].DB_MAX_OUTPUT_PORT_TYPE
keycode[5] <= sw_data_out[5].DB_MAX_OUTPUT_PORT_TYPE
keycode[6] <= sw_data_out[6].DB_MAX_OUTPUT_PORT_TYPE
keycode[7] <= sw_data_out[7].DB_MAX_OUTPUT_PORT_TYPE
switch_se[1] <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
switch_se[2] <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
switch_se[3] <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
switch_se[4] <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
switch_se[5] <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
switch_se[6] <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
switch_se[7] <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
switch_se[8] <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
switch_se[9] <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
search_start_cmd => int_trig_en~1.OUTPUTSELECT
search_stop_cmd => int_trig_en~0.OUTPUTSELECT


|fpga313czkz|search_panel:m1|scan_reg8:scan0
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[7]~reg0.CLK
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
ena => q[6]~reg0.ENA
ena => q[5]~reg0.ENA
ena => q[4]~reg0.ENA
ena => q[3]~reg0.ENA
ena => q[2]~reg0.ENA
ena => q[1]~reg0.ENA
ena => q[0]~reg0.ENA
ena => q[7]~reg0.ENA
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fpga313czkz|search_panel:m1|scan_reg8:scan1
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[7]~reg0.CLK
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
ena => q[6]~reg0.ENA
ena => q[5]~reg0.ENA
ena => q[4]~reg0.ENA
ena => q[3]~reg0.ENA
ena => q[2]~reg0.ENA
ena => q[1]~reg0.ENA
ena => q[0]~reg0.ENA
ena => q[7]~reg0.ENA
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fpga313czkz|search_panel:m1|scan_reg8:scan2
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[7]~reg0.CLK
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
ena => q[6]~reg0.ENA
ena => q[5]~reg0.ENA
ena => q[4]~reg0.ENA
ena => q[3]~reg0.ENA
ena => q[2]~reg0.ENA
ena => q[1]~reg0.ENA
ena => q[0]~reg0.ENA
ena => q[7]~reg0.ENA
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fpga313czkz|search_panel:m1|scan_reg8:scan3
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[7]~reg0.CLK
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
ena => q[6]~reg0.ENA
ena => q[5]~reg0.ENA
ena => q[4]~reg0.ENA
ena => q[3]~reg0.ENA
ena => q[2]~reg0.ENA
ena => q[1]~reg0.ENA
ena => q[0]~reg0.ENA
ena => q[7]~reg0.ENA
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fpga313czkz|search_panel:m1|scan_reg8:scan4
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[7]~reg0.CLK
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
ena => q[6]~reg0.ENA
ena => q[5]~reg0.ENA
ena => q[4]~reg0.ENA
ena => q[3]~reg0.ENA
ena => q[2]~reg0.ENA
ena => q[1]~reg0.ENA
ena => q[0]~reg0.ENA
ena => q[7]~reg0.ENA
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fpga313czkz|search_panel:m1|scan_reg8:scan5
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[7]~reg0.CLK
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
ena => q[6]~reg0.ENA
ena => q[5]~reg0.ENA
ena => q[4]~reg0.ENA
ena => q[3]~reg0.ENA
ena => q[2]~reg0.ENA
ena => q[1]~reg0.ENA
ena => q[0]~reg0.ENA
ena => q[7]~reg0.ENA
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE