fpga313czkz.map.qmsg

windowsxp/2000下驱动程序开发软件winddriver6.0

{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ttl_in search_panel.v(161) " "Warning: Verilog HDL Always Construct warning at search_panel.v(161): variable \"ttl_in\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "search_panel.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/search_panel.v" 161 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scan_reg8 search_panel:m1\|scan_reg8:scan0 " "Info: Elaborating entity \"scan_reg8\" for hierarchy \"search_panel:m1\|scan_reg8:scan0\"" {  } { { "search_panel.v" "scan0" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/search_panel.v" 142 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ttl128bit_dq search_panel:m1\|ttl128bit_dq:ttl_ram " "Info: Elaborating entity \"ttl128bit_dq\" for hierarchy \"search_panel:m1\|ttl128bit_dq:ttl_ram\"" {  } { { "search_panel.v" "ttl_ram" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/search_panel.v" 180 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus5.0/libraries/megafunctions/lpm_ram_dq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartus5.0/libraries/megafunctions/lpm_ram_dq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dq " "Info: Found entity 1: lpm_ram_dq" {  } { { "lpm_ram_dq.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/lpm_ram_dq.tdf" 57 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq search_panel:m1\|ttl128bit_dq:ttl_ram\|lpm_ram_dq:lpm_ram_dq_component " "Info: Elaborating entity \"lpm_ram_dq\" for hierarchy \"search_panel:m1\|ttl128bit_dq:ttl_ram\|lpm_ram_dq:lpm_ram_dq_component\"" {  } { { "ttl128bit_dq.v" "lpm_ram_dq_component" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/ttl128bit_dq.v" 68 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus5.0/libraries/megafunctions/altram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartus5.0/libraries/megafunctions/altram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altram " "Info: Found entity 1: altram" {  } { { "altram.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/altram.tdf" 88 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram search_panel:m1\|ttl128bit_dq:ttl_ram\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram " "Info: Elaborating entity \"altram\" for hierarchy \"search_panel:m1\|ttl128bit_dq:ttl_ram\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\"" {  } { { "lpm_ram_dq.tdf" "sram" { Text "d:/quartus5.0/libraries/megafunctions/lpm_ram_dq.tdf" 98 6 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "main main:m2 " "Info: Elaborating entity \"main\" for hierarchy \"main:m2\"" {  } { { "fpga313czkz.v" "m2" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 150 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lamp lamp:m3 " "Info: Elaborating entity \"lamp\" for hierarchy \"lamp:m3\"" {  } { { "fpga313czkz.v" "m3" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 165 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lighten_en lamp:m3\|lighten_en:u1 " "Info: Elaborating entity \"lighten_en\" for hierarchy \"lamp:m3\|lighten_en:u1\"" {  } { { "lamp.v" "u1" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/lamp.v" 72 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lamp_light lamp:m3\|lamp_light:u2 " "Info: Elaborating entity \"lamp_light\" for hierarchy \"lamp:m3\|lamp_light:u2\"" {  } { { "lamp.v" "u2" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/lamp.v" 80 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lreg lamp:m3\|lamp_light:u2\|lreg:g1 " "Info: Elaborating entity \"lreg\" for hierarchy \"lamp:m3\|lamp_light:u2\|lreg:g1\"" {  } { { "lamp_light.v" "g1" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/lamp_light.v" 47 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "parallel_port parallel_port:m4 " "Info: Elaborating entity \"parallel_port\" for hierarchy \"parallel_port:m4\"" {  } { { "fpga313czkz.v" "m4" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 213 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "Selctin_1 parallel_port.v(136) " "Info: (10035) Verilog HDL or VHDL information at parallel_port.v(136): object \"Selctin_1\" declared but not used" {  } { { "parallel_port.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/parallel_port.v" 136 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "search_panel:m1\|scan_cnt\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"search_panel:m1\|scan_cnt\[0\]~4\"" {  } { { "search_panel.v" "scan_cnt\[0\]~4" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/search_panel.v" 109 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "parallel_port:m4\|delay_count0\[0\]~48 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"parallel_port:m4\|delay_count0\[0\]~48\"" {  } { { "parallel_port.v" "delay_count0\[0\]~48" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/parallel_port.v" 129 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt1\[0\]~16 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt1\[0\]~16\"" {  } { { "fpga313czkz.v" "cnt1\[0\]~16" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 87 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus5.0/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartus5.0/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus5.0/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartus5.0/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/quartus5.0/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}