fpga313czkz.map.qmsg

windowsxp/2000下驱动程序开发软件winddriver6.0

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 17 09:09:10 2006 " "Info: Processing started: Mon Jul 17 09:09:10 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fpga313czkz -c fpga313czkz " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fpga313czkz -c fpga313czkz" {  } {  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "fpga313czkz.v(83) " "Warning: (10273) Verilog HDL warning at fpga313czkz.v(83): extended using \"x\" or \"z\"" {  } { { "fpga313czkz.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 83 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fpga313czkz.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fpga313czkz.v" { { "Info" "ISGN_ENTITY_NAME" "1 fpga313czkz " "Info: Found entity 1: fpga313czkz" {  } { { "fpga313czkz.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 35 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lamp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lamp.v" { { "Info" "ISGN_ENTITY_NAME" "1 lamp " "Info: Found entity 1: lamp" {  } { { "lamp.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/lamp.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lamp_light.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lamp_light.v" { { "Info" "ISGN_ENTITY_NAME" "1 lamp_light " "Info: Found entity 1: lamp_light" {  } { { "lamp_light.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/lamp_light.v" 32 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lighten_en.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lighten_en.v" { { "Info" "ISGN_ENTITY_NAME" "1 lighten_en " "Info: Found entity 1: lighten_en" {  } { { "lighten_en.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/lighten_en.v" 37 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lreg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lreg.v" { { "Info" "ISGN_ENTITY_NAME" "1 lreg " "Info: Found entity 1: lreg" {  } { { "lreg.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/lreg.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.v" { { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" {  } { { "main.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/main.v" 37 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IVRFX_VERI_VAR_DIF_ONLY_IN_CASE" "Selctin_1 selctin_1 parallel_port.v(136) " "Info: (10281) Verilog HDL information at parallel_port.v(136): variable name \"Selctin_1\" and variable name \"selctin_1\" should not differ only in case" {  } { { "parallel_port.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/parallel_port.v" 136 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "parallel_port.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file parallel_port.v" { { "Info" "ISGN_ENTITY_NAME" "1 parallel_port " "Info: Found entity 1: parallel_port" {  } { { "parallel_port.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/parallel_port.v" 33 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "scan_reg8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file scan_reg8.v" { { "Info" "ISGN_ENTITY_NAME" "1 scan_reg8 " "Info: Found entity 1: scan_reg8" {  } { { "scan_reg8.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/scan_reg8.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "search_panel.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file search_panel.v" { { "Info" "ISGN_ENTITY_NAME" "1 search_panel " "Info: Found entity 1: search_panel" {  } { { "search_panel.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/search_panel.v" 56 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ttl128bit_dq.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ttl128bit_dq.v" { { "Info" "ISGN_ENTITY_NAME" "1 ttl128bit_dq " "Info: Found entity 1: ttl128bit_dq" {  } { { "ttl128bit_dq.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/ttl128bit_dq.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fpga313czkz " "Info: Elaborating entity \"fpga313czkz\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "search_panel search_panel:m1 " "Info: Elaborating entity \"search_panel\" for hierarchy \"search_panel:m1\"" {  } { { "fpga313czkz.v" "m1" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/fpga313czkz.v" 120 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ttl_in search_panel.v(155) " "Warning: Verilog HDL Always Construct warning at search_panel.v(155): variable \"ttl_in\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "search_panel.v" "" { Text "E:/my_work/313/操作控制板_归档/HARDWARE/EPLD/CPV3 FIREWARE/ver6.0/search_panel.v" 155 0 0 } }  } 0}