📄 fpga313czkz.hif
字号:
Version 5.0 Build 148 04/26/2005 SJ Full Version
17
837
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
fpga313czkz
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fpga313czkz.v
1150275584
7
# storage
db|fpga313czkz.(0).cnf
db|fpga313czkz.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
param.v
1139562320
}
# hierarchies {
|
}
# end
# entity
search_panel
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
search_panel.v
1150255674
7
# storage
db|fpga313czkz.(1).cnf
db|fpga313czkz.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
NUM_OF_SWITCH
72
PARAMETER_DEC
DEF
TIME_FOR_DELAY
00000000000000001100001101010000
PARAMETER_BIN
DEF
IDLE
0000
PARAMETER_BIN
DEF
LOCK_TTL
0001
PARAMETER_BIN
DEF
JUDGE_TTL_REG
0010
PARAMETER_BIN
DEF
SAVE_TTL_VALUE
0011
PARAMETER_BIN
DEF
JUDGE_TTL_END
0100
PARAMETER_BIN
DEF
ASSEMBLE_DATA
0101
PARAMETER_BIN
DEF
INT
0110
PARAMETER_BIN
DEF
WAIT_ACK
0111
PARAMETER_BIN
DEF
INITIONLIZE_RAM
1000
PARAMETER_BIN
DEF
}
# include_file {
param.v
1139562320
}
# hierarchies {
search_panel:m1
}
# end
# entity
scan_reg8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
scan_reg8.v
1133766608
7
# storage
db|fpga313czkz.(2).cnf
db|fpga313czkz.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
search_panel:m1|scan_reg8:scan0
search_panel:m1|scan_reg8:scan1
search_panel:m1|scan_reg8:scan2
search_panel:m1|scan_reg8:scan3
search_panel:m1|scan_reg8:scan4
search_panel:m1|scan_reg8:scan5
search_panel:m1|scan_reg8:scan6
search_panel:m1|scan_reg8:scan7
search_panel:m1|scan_reg8:scan8
}
# end
# entity
ttl128bit_dq
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ttl128bit_dq.v
1136514298
7
# storage
db|fpga313czkz.(3).cnf
db|fpga313czkz.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
search_panel:m1|ttl128bit_dq:ttl_ram
}
# end
# entity
lpm_ram_dq
# case_insensitive
# source_file
d:|quartus5.0|libraries|megafunctions|lpm_ram_dq.tdf
1114012454
6
# storage
db|fpga313czkz.(4).cnf
db|fpga313czkz.(4).cnf
# user_parameter {
LPM_WIDTH
1
PARAMETER_DEC
USR
LPM_WIDTHAD
7
PARAMETER_DEC
USR
LPM_NUMWORDS
128
PARAMETER_UNKNOWN
DEF
LPM_INDATA
REGISTERED
PARAMETER_UNKNOWN
USR
LPM_ADDRESS_CONTROL
REGISTERED
PARAMETER_UNKNOWN
USR
LPM_OUTDATA
UNREGISTERED
PARAMETER_UNKNOWN
USR
LPM_FILE
ttl128.mif
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
address
address
address
address
address
address
address
data
inclock
q
we
}
# include_file {
d:|quartus5.0|libraries|megafunctions|altram.inc
1107573384
d:|quartus5.0|libraries|megafunctions|lpm_mux.inc
1107574776
d:|quartus5.0|libraries|megafunctions|lpm_decode.inc
1107574570
d:|quartus5.0|libraries|megafunctions|aglobal50.inc
1114012420
}
# hierarchies {
search_panel:m1|ttl128bit_dq:ttl_ram|lpm_ram_dq:lpm_ram_dq_component
}
# end
# entity
altram
# case_insensitive
# source_file
d:|quartus5.0|libraries|megafunctions|altram.tdf
1114012438
6
# storage
db|fpga313czkz.(5).cnf
db|fpga313czkz.(5).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH
1
PARAMETER_UNKNOWN
USR
AD_WIDTH
7
PARAMETER_UNKNOWN
USR
NUMWORDS
128
PARAMETER_UNKNOWN
USR
FILE
ttl128.mif
PARAMETER_UNKNOWN
USR
REGISTERINPUTMODE
ALL
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
2048
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
}
# used_port {
we
data0
address0
address1
address2
address3
address4
address5
address6
clocki
q0
}
# include_file {
d:|quartus5.0|libraries|megafunctions|lpm_mux.inc
1107574776
d:|quartus5.0|libraries|megafunctions|lpm_decode.inc
1107574570
d:|quartus5.0|libraries|megafunctions|aglobal50.inc
1114012420
d:|quartus5.0|libraries|megafunctions|altqpram.inc
1107573362
d:|quartus5.0|libraries|megafunctions|altsyncram.inc
1107573506
d:|quartus5.0|libraries|others|maxplus2|memmodes.inc
1107579370
}
# memory_file {
ttl128.mif
1133855864
}
# hierarchies {
search_panel:m1|ttl128bit_dq:ttl_ram|lpm_ram_dq:lpm_ram_dq_component|altram:sram
}
# end
# entity
main
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
main.v
1150257314
7
# storage
db|fpga313czkz.(6).cnf
db|fpga313czkz.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
JudgeParallelFull
00000
PARAMETER_BIN
DEF
AckParallel
00001
PARAMETER_BIN
DEF
ExecuteBackbyte
00010
PARAMETER_BIN
DEF
WriteToLampModule
00011
PARAMETER_BIN
DEF
ControlByteTransmitWait
00100
PARAMETER_BIN
DEF
LoadControlByteToSerialTransmitBuffer
00101
PARAMETER_BIN
DEF
ControlByteTransmit
00110
PARAMETER_BIN
DEF
ControlByteTransmitControl
00111
PARAMETER_BIN
DEF
LoadResendByte
01000
PARAMETER_BIN
DEF
LoadSelfByte
01001
PARAMETER_BIN
DEF
LoadResetByte
01010
PARAMETER_BIN
DEF
LoadSendAllByte
01011
PARAMETER_BIN
DEF
LoadSearchStart
01100
PARAMETER_BIN
DEF
LoadSearchStop
01101
PARAMETER_BIN
DEF
LoadRevErrByte
01110
PARAMETER_BIN
DEF
LoadControlByte
01111
PARAMETER_BIN
DEF
AckSwitch
10000
PARAMETER_BIN
DEF
}
# include_file {
param.v
1139562320
}
# hierarchies {
main:m2
}
# end
# entity
lamp
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lamp.v
1139562618
7
# storage
db|fpga313czkz.(7).cnf
db|fpga313czkz.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
param.v
1139562320
}
# hierarchies {
lamp:m3
}
# end
# entity
lighten_en
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lighten_en.v
1139562680
7
# storage
db|fpga313czkz.(8).cnf
db|fpga313czkz.(8).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
param.v
1139562320
}
# hierarchies {
lamp:m3|lighten_en:u1
}
# end
# entity
lamp_light
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lamp_light.v
1139562634
7
# storage
db|fpga313czkz.(9).cnf
db|fpga313czkz.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
param.v
1139562320
}
# hierarchies {
lamp:m3|lamp_light:u2
}
# end
# entity
lreg
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lreg.v
1136962132
7
# storage
db|fpga313czkz.(10).cnf
db|fpga313czkz.(10).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
lamp:m3|lamp_light:u2|lreg:g1
lamp:m3|lamp_light:u2|lreg:g2
lamp:m3|lamp_light:u2|lreg:g3
lamp:m3|lamp_light:u2|lreg:g4
lamp:m3|lamp_light:u2|lreg:g5
lamp:m3|lamp_light:u2|lreg:g6
lamp:m3|lamp_light:u2|lreg:g7
lamp:m3|lamp_light:u2|lreg:g8
lamp:m3|lamp_light:u2|lreg:g9
lamp:m3|lamp_light:u2|lreg:g10
lamp:m3|lamp_light:u2|lreg:g11
lamp:m3|lamp_light:u2|lreg:g12
lamp:m3|lamp_light:u2|lreg:g13
lamp:m3|lamp_light:u2|lreg:g14
lamp:m3|lamp_light:u2|lreg:g15
lamp:m3|lamp_light:u2|lreg:g16
lamp:m3|lamp_light:u2|lreg:g17
lamp:m3|lamp_light:u2|lreg:g18
lamp:m3|lamp_light:u2|lreg:g19
lamp:m3|lamp_light:u2|lreg:g20
lamp:m3|lamp_light:u2|lreg:g21
lamp:m3|lamp_light:u2|lreg:g22
lamp:m3|lamp_light:u2|lreg:g23
lamp:m3|lamp_light:u2|lreg:g24
lamp:m3|lamp_light:u2|lreg:g25
lamp:m3|lamp_light:u2|lreg:g26
lamp:m3|lamp_light:u2|lreg:g27
lamp:m3|lamp_light:u2|lreg:g28
lamp:m3|lamp_light:u2|lreg:g29
lamp:m3|lamp_light:u2|lreg:g30
lamp:m3|lamp_light:u2|lreg:g31
lamp:m3|lamp_light:u2|lreg:g32
lamp:m3|lamp_light:u2|lreg:g33
lamp:m3|lamp_light:u2|lreg:g34
lamp:m3|lamp_light:u2|lreg:g35
lamp:m3|lamp_light:u2|lreg:g36
lamp:m3|lamp_light:u2|lreg:g37
lamp:m3|lamp_light:u2|lreg:g38
lamp:m3|lamp_light:u2|lreg:g39
lamp:m3|lamp_light:u2|lreg:g40
lamp:m3|lamp_light:u2|lreg:g41
lamp:m3|lamp_light:u2|lreg:g42
lamp:m3|lamp_light:u2|lreg:g43
lamp:m3|lamp_light:u2|lreg:g44
lamp:m3|lamp_light:u2|lreg:g45
lamp:m3|lamp_light:u2|lreg:g46
lamp:m3|lamp_light:u2|lreg:g47
lamp:m3|lamp_light:u2|lreg:g48
lamp:m3|lamp_light:u2|lreg:g49
lamp:m3|lamp_light:u2|lreg:g50
lamp:m3|lamp_light:u2|lreg:g51
lamp:m3|lamp_light:u2|lreg:g52
lamp:m3|lamp_light:u2|lreg:g53
lamp:m3|lamp_light:u2|lreg:g54
lamp:m3|lamp_light:u2|lreg:g55
lamp:m3|lamp_light:u2|lreg:g56
lamp:m3|lamp_light:u2|lreg:g57
lamp:m3|lamp_light:u2|lreg:g58
lamp:m3|lamp_light:u2|lreg:g59
lamp:m3|lamp_light:u2|lreg:g60
lamp:m3|lamp_light:u2|lreg:g61
lamp:m3|lamp_light:u2|lreg:g62
lamp:m3|lamp_light:u2|lreg:g63
lamp:m3|lamp_light:u2|lreg:g64
lamp:m3|lamp_light:u2|lreg:g65
}
# end
# entity
parallel_port
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
parallel_port.v
1150275106
7
# storage
db|fpga313czkz.(11).cnf
db|fpga313czkz.(11).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
delay_time0
0000000001100100
PARAMETER_BIN
DEF
RD_IDLE
000
PARAMETER_BIN
DEF
RD_START
001
PARAMETER_BIN
DEF
RD_END
010
PARAMETER_BIN
DEF
delay_time1
0000000111110100
PARAMETER_BIN
DEF
TR_IDLE
000
PARAMETER_BIN
DEF
TR_START
001
PARAMETER_BIN
DEF
TR_END
010
PARAMETER_BIN
DEF
}
# include_file {
param.v
1139562320
}
# hierarchies {
parallel_port:m4
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
d:|quartus5.0|libraries|megafunctions|lpm_counter.tdf
1114012448
6
# storage
db|fpga313czkz.(12).cnf
db|fpga313czkz.(12).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
4
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
}
# used_port {
aclr
clock
q0
q1
q2
q3
sclr
}
# include_file {
d:|quartus5.0|libraries|megafunctions|lpm_decode.inc
1107574570
d:|quartus5.0|libraries|megafunctions|aglobal50.inc
1114012420
d:|quartus5.0|libraries|megafunctions|lpm_constant.inc
1107574524
d:|quartus5.0|libraries|megafunctions|lpm_add_sub.inc
1107574408
d:|quartus5.0|libraries|megafunctions|cmpconst.inc
1107573980
d:|quartus5.0|libraries|megafunctions|lpm_compare.inc
1107574500
d:|quartus5.0|libraries|megafunctions|lpm_counter.inc
1107574548
d:|quartus5.0|libraries|megafunctions|dffeea.inc
1107574164
d:|quartus5.0|libraries|megafunctions|alt_synch_counter.inc
1107572664
d:|quartus5.0|libraries|megafunctions|alt_synch_counter_f.inc
1107572680
d:|quartus5.0|libraries|megafunctions|alt_counter_f10ke.inc
1107572320
d:|quartus5.0|libraries|megafunctions|alt_counter_stratix.inc
1107572334
}
# end
# entity
alt_counter_f10ke
# case_insensitive
# source_file
d:|quartus5.0|libraries|megafunctions|alt_counter_f10ke.tdf
1114012450
6
# storage
db|fpga313czkz.(13).cnf
db|fpga313czkz.(13).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
4
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
USR
LPM_SVALUE
15
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
15
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CASCADE_CHAIN_LENGTH
2
CASCADE_CHAIN_LENGTH
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
}
# used_port {
clock
aclr
sclr
q0
q1
q2
q3
cout
}
# include_file {
d:|quartus5.0|libraries|megafunctions|aglobal50.inc
1114012420
d:|quartus5.0|libraries|megafunctions|lpm_constant.inc
1107574524
d:|quartus5.0|libraries|megafunctions|lpm_compare.inc
1107574500
d:|quartus5.0|libraries|megafunctions|flex10ke_lcell.inc
1107574288
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
d:|quartus5.0|libraries|megafunctions|lpm_counter.tdf
1114012448
6
# storage
db|fpga313czkz.(14).cnf
db|fpga313czkz.(14).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
}
# used_port {
clk_en
clock
cnt_en
q0
q10
q11
q12
q13
q14
q15
q1
q2
q3
q4
q5
q6
q7
q8
q9
sclr
}
# include_file {
d:|quartus5.0|libraries|megafunctions|lpm_decode.inc
1107574570
d:|quartus5.0|libraries|megafunctions|aglobal50.inc
1114012420
d:|quartus5.0|libraries|megafunctions|lpm_constant.inc
1107574524
d:|quartus5.0|libraries|megafunctions|lpm_add_sub.inc
1107574408
d:|quartus5.0|libraries|megafunctions|cmpconst.inc
1107573980
d:|quartus5.0|libraries|megafunctions|lpm_compare.inc
1107574500
d:|quartus5.0|libraries|megafunctions|lpm_counter.inc
1107574548
d:|quartus5.0|libraries|megafunctions|dffeea.inc
1107574164
d:|quartus5.0|libraries|megafunctions|alt_synch_counter.inc
1107572664
d:|quartus5.0|libraries|megafunctions|alt_synch_counter_f.inc
1107572680
d:|quartus5.0|libraries|megafunctions|alt_counter_f10ke.inc
1107572320
d:|quartus5.0|libraries|megafunctions|alt_counter_stratix.inc
1107572334
}
# end
# entity
alt_counter_f10ke
# case_insensitive
# source_file
d:|quartus5.0|libraries|megafunctions|alt_counter_f10ke.tdf
1114012450
6
# storage
db|fpga313czkz.(15).cnf
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