scan_reg8.v

来自「windowsxp/2000下驱动程序开发软件winddriver6.0」· Verilog 代码 · 共 13 行

module scan_reg8 (clk,d,ena,q);
input clk;
input [7:0]	d;
input ena;
output [7:0]	q;
reg [7:0]	 q;

always @(posedge clk)
	if(ena)
		q<=d;
	else
		q<=q;
endmodule