📄 main.v
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// +FHDR----------------------------------------------------------
// Copyright (C) 2006 Casic23
// Casic23 Confidential Proprietary.
// ----------------------------------------------------------------
// FILE NAME : main.v
// TYPE : sub Module
// DEPARTMENT : Casic23 team 7
// AUTHOR : jing gang
// AUTHOR EMAIL : jg_xian@yahoo.com.cn
// ---------------------------------------------------------------
// Realease histroy
// VERSION DATE AUTHOR DESCRIPTION
// ver1.01 JAN.12 2006 Jing Gang initial version
// ver1.1 JAN.25 2006 Jing Gang
//------增加search_start_cmd，search_stop_cmd两个命令
//------ver1.2 Feb.2 2006 Jing Gang
//------将ExecuteBackbyte的几个命令不用反馈，命令的体现在于相应的寄存器的变化，
//------所以不需要向主机发送返回字，所以也不用置控制字传送标志位。
// ---------------------------------------------------------------
// KEYWORDS : TLP313
// ---------------------------------------------------------------
// PURPOSE : main state machine.
// ---------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNIT
// ---------------------------------------------------------------
// RESUSE ISSUES
// Reset Strategy :
// Coclk Domain :
// Critical Timing :
// Test Feature :
// Asynchronous I/F:
// Scan Methodoly :
// Instantiations :
// Others :
// - FHDR----------------------------------------------------------
module main(
clk,
sw_code,
sw_int,
sw_ack,
//sw_check,
lamp_wr,
lamp_data,
parallel_rd,
parallel_busy,
parallel_full,
parallel_tr,
parallel_send,
parallel_ack,
reset_n,
search_start_cmd,
search_stop_cmd
);
`include "param.v"
input clk; // 输入时钟
input [`WIDTH_KEYCODE-1:0] sw_code; // 输入的键盘编码
input sw_int; // 键盘中断请求
output sw_ack; // 主状态机对键盘中断请求的应答
output lamp_wr; // 点灯命令
output [`WIDTH_LAMP_DATA-1:0] lamp_data; //点灯数据
input parallel_busy; //并口发送忙信号
input parallel_full; // 并口接受满信号
input [`WIDTH_PARADATA-1:0] parallel_rd; // 主状态机接受并口数据总线
output [`WIDTH_PARADATA-1:0] parallel_tr; // 主状态机发送并口数据总线
output parallel_send; // 并口发送数据命令
output parallel_ack; // 并口对接受满信号的应答
output reset_n; //产生复位信号
output search_start_cmd; //搜索开始命令
output search_stop_cmd; //搜索停止命令
assign search_start_cmd=SearchStart;
assign search_stop_cmd=SearchStop;
reg sw_ack;
reg lamp_wr;
wire [`WIDTH_LAMP_DATA-1:0] lamp_data;
reg [`WIDTH_LAMP_DATA-1:0] backbyte;
assign lamp_data=backbyte;
wire [`WIDTH_PARADATA-1:0] parallel_tr;
reg [`WIDTH_PARADATA-1:0] ParallelTransmitBuffer;// 并口发送数据缓冲
assign parallel_tr=ParallelTransmitBuffer;
reg parallel_send;
reg parallel_ack;
reg ResetStrobe;// reset信号产生命令
reg SelfCheck; // 自检产生命令
reg SendAll; //
reg ReSend; //
reg SearchStart;
reg SearchStop;
reg ControlByteTransmitFlag; // 控制字发送标志
reg [7:0] ControlByte; // 控制字
reg reset_reg;
reg [4:0] reset_cnt;
wire reset_n;
assign reset_n=!reset_reg;
reg [4:0] mach_next;
parameter JudgeParallelFull=5'd0,// 判断接受满状态
AckParallel=5'd1, // 应答并口接受满状态
ExecuteBackbyte=5'd2, //检测执行收到并口数据状态
WriteToLampModule=5'd3, // 点灯状态
ControlByteTransmitWait=5'd4, // 控制字传输等待状态
LoadControlByteToSerialTransmitBuffer=5'd5, // 发送控制字状态
ControlByteTransmit=5'd6, //控制字传输状态
ControlByteTransmitControl=5'd7, //控制字传输控制状态
LoadResendByte=5'd8, // 响应ResendByte命令状态
LoadSelfByte=5'd9, // 响应LoadSelfByte命令状态
LoadResetByte=5'd10, // 响应LoadResetByte命令状态
LoadSendAllByte=5'd11, // 响应LoadSendAllByte命令状态
LoadSearchStart=5'd12, // 响应LoadSearchStart命令状态
LoadSearchStop=5'd13, // 响应LoadSearchStop命令状态
LoadRevErrByte=5'd14, // 响应LoadSendAllByte命令状态
LoadControlByte=5'd15,// 响应中断请求命令状态
AckSwitch=5'd16; // 中断应答状态
// 主状态机初始状态是JudgeParallelFull状态，检测并口的接受满标志，若满则发出应答信号
// 同时对接受来的并口数据做检测，若是控制命令字则置响应的命令标志，接着跳到相应的发送
// 命令状态，并置发送标志位，若是数据则跳到点灯的状态，也置发送控制位。当不满时则跳到
// 控制字传输状态，检测控制字传输标志是否置位，当置位时，就跳到控制字发送等待状态，若
// 没有置位则按顺序检测响应各命令标志和中断请求信号。当有中断请求时，则置传送控制位并
// 清中断。当处于发送控制等待状态时，若并口不忙，则发出发送命令并清发送传送标志。
always @(posedge clk )
begin
case(mach_next)
JudgeParallelFull:
if(parallel_full)
begin
parallel_ack<=1'b1; //
mach_next<=AckParallel;
end
else
begin
parallel_ack<=1'b0;
mach_next<=ControlByteTransmitControl;
end
AckParallel:
begin
parallel_ack<=1'b0;
backbyte<=parallel_rd;
mach_next<=ExecuteBackbyte;
end
ExecuteBackbyte:
begin
if(backbyte[7:4]==4'hf)
begin
case(backbyte[3:0])
4'd0: begin ResetStrobe<=1'b1; reset_cnt<=5'd0;mach_next<=JudgeParallelFull; end // reset command
4'd1: begin SelfCheck<=1'b1; mach_next<=JudgeParallelFull;end // self check command
4'd2: begin SendAll<=1'b1; mach_next<=JudgeParallelFull;end // sendall command
4'd3: begin ReSend<=1'b1; mach_next<=JudgeParallelFull;end // resend command
4'd4: begin SearchStart<=1'b1; mach_next<=JudgeParallelFull;end
4'd5: begin SearchStop<=1'b1; mach_next<=JudgeParallelFull;end
default: begin mach_next<=JudgeParallelFull; end // nop command
endcase
end
else
begin
mach_next<=WriteToLampModule;
lamp_wr<=1'b1;
end
end
WriteToLampModule:
begin
lamp_wr<=1'b0;
mach_next<=JudgeParallelFull;
end
ControlByteTransmitWait:
begin
if(parallel_busy)
mach_next<=JudgeParallelFull;
else
begin
mach_next<=LoadControlByteToSerialTransmitBuffer;
ParallelTransmitBuffer<=ControlByte[7:0];
ControlByteTransmitFlag<=1'b0;
end
end
LoadControlByteToSerialTransmitBuffer:
begin
parallel_send<=1'b1;
mach_next<=ControlByteTransmit;
end
ControlByteTransmit:
begin
parallel_send<=1'b0;
mach_next<=JudgeParallelFull;
end
ControlByteTransmitControl:
begin
if(ControlByteTransmitFlag)
mach_next<=ControlByteTransmitWait;
else
mach_next<=LoadResendByte;
end
LoadResendByte:
begin
if(ReSend)
begin
ReSend<=1'b0;
ControlByteTransmitFlag<=1'b0;
mach_next<=JudgeParallelFull;
end
else
mach_next<=LoadSelfByte;
end
LoadSelfByte:
begin
if(SelfCheck)
begin
SelfCheck<=1'b0;
//ControlByte<=8'd36;
ControlByteTransmitFlag<=1'b0;
mach_next<=JudgeParallelFull;
end
else
mach_next<=LoadResetByte;
end
LoadResetByte:
begin
if(ResetStrobe)
begin
if(reset_cnt>=5'd5 & reset_cnt<=5'd25 )
reset_reg<=1'b1;
else
reset_reg<=1'b0;
if(reset_cnt<=5'd30)
begin
reset_cnt<=reset_cnt+5'd1;
mach_next<=LoadResetByte;
end
else
begin
ResetStrobe<=1'b0;
// ControlByte<=8'h36;
ControlByteTransmitFlag<=1'b0;
mach_next<=JudgeParallelFull;
//
parallel_ack <= 1'b0;
backbyte <= 8'd0;
//ResetStrobe <= 1'b0;
SelfCheck <= 1'b0;
SendAll <= 1'b0;
ReSend <= 1'b0;
SearchStart <= 1'b0;
SearchStop <= 1'b0;
lamp_wr <= 1'b0;
ParallelTransmitBuffer <= 8'd0;
//ControlByteTransmitFlag <= 1'b0;
parallel_send <= 1'b0;
sw_ack <= 1'b0;
//
end
end
else
mach_next<=LoadSendAllByte;
end
LoadSendAllByte:
begin
if(SendAll)
begin
SendAll<=1'b0;
//ControlByte<=8'h36;
ControlByteTransmitFlag<=1'b0;
mach_next<=JudgeParallelFull;
end
else
mach_next<=LoadSearchStart;
end
LoadSearchStart:
begin
if(SearchStart)
begin
SearchStart<=1'b0;
//ControlByte<=8'h36;
ControlByteTransmitFlag<=1'b0;
mach_next<=JudgeParallelFull;
end
else
mach_next<=LoadSearchStop;
end
LoadSearchStop:
begin
if(SearchStop)
begin
SearchStop<=1'b0;
//ControlByte<=8'h36;
ControlByteTransmitFlag<=1'b0;
mach_next<=JudgeParallelFull;
end
else
mach_next<=LoadControlByte;
end
LoadControlByte:
begin
//if(sw_int && (parallel_busy!=1))
if(sw_int)
begin
ControlByte<=sw_code;
ControlByteTransmitFlag<=1'b1;
mach_next<=AckSwitch;
sw_ack<=1'b1;
end
else
begin
sw_ack<=1'b0;
mach_next<=JudgeParallelFull;
end
end
AckSwitch:
begin
sw_ack<=1'b0;
mach_next<=JudgeParallelFull;
end
default: mach_next<=JudgeParallelFull;
endcase
end
endmodule
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