parallel_port.v

windowsxp/2000下驱动程序开发软件winddriver6.0

// +FHDR----------------------------------------------------------
// Copyright (C) 2006 Casic23
// Casic23 Confidential Proprietary.
// ----------------------------------------------------------------
// FILE NAME : parallel_port.v
// TYPE : TOP Module
// DEPARTMENT : Casic23 team 7
// AUTHOR : jing gang
// AUTHOR EMAIL : [e-mail]
// ---------------------------------------------------------------
// Realease histroy
// VERSION DATE AUTHOR DESCRIPTION
// 		ver1.01 JAN.12 2006 Jing Gang initial version 
// ---------------------------------------------------------------
// KEYWORDS	: TLP313 
// ---------------------------------------------------------------
// PURPOSE	: through the gernral parallel port ,transmit or receive 
// data between the CZKZ board with host computer .  
// ---------------------------------------------------------------
// PARAMETERS
// 		 PARAM NAME		RANGE	:	DESCRIPTION	:	DEFAULT	: VA UNIT
// ---------------------------------------------------------------
// RESUSE ISSUES
//		Reset Strategy	:
//		Coclk Domain 	:
//		Critical Timing	:
//		Test Feature	:
//		Asynchronous I/F:
//		Scan Methodoly	:
//		Instantiations	:
//		Others			:
// - FHDR----------------------------------------------------------
module parallel_port(
			                clk,
			                reset_n,
			
			                rd_full,
			                rd_ack,
			                parabus_busy,
			                send_cmd,
			                parallel_tr,
			                parallel_rd,
			                para_dir,
			                para_datain,
			                para_dataout,
			
			                //strobein,
			                //autoin,
			                //intin,
			                selctin,
			
			                ackout
			                //busyout,
			                //peout,
			                //slctout
			                //errout
			              );
			
`include "param.v"

input clk; // 输入时钟
input reset_n; // 异步复位

output rd_full; // 接受满标志
input rd_ack; // 主状态机接受应答
output parabus_busy; //并口发送忙信号
input send_cmd; // 发送命令
input [`WIDTH_PARADATA-1:0] parallel_tr; // 主状态机发送数据总线
output [`WIDTH_PARADATA-1:0] parallel_rd; // 主状态机接受数据总线

output para_dir; // 发送、接受方向控制
input[`WIDTH_PARADATA-1:0] para_datain; // 并口输入数据总线
output[`WIDTH_PARADATA-1:0] para_dataout;	// 并口输出数据总线
//input strobein; // 通用并口输入STROBE信号
//input autoin; // 通用并口输入AUTO信号
//input intin; // 通用并口输入INIT信号
input selctin; // 通用并口输入SELECT信号
output ackout; // 通用并口输出ACK信号
//output busyout; // 通用并口输入BUSY信号
//output peout; // 通用并口输入PE信号
//output slctout; // 通用并口输入SLCT信号
//output errout; // 通用并口输入ERR信号

wire ackout;
reg selctin_1;
	
reg [`WIDTH_PARADATA-1:0] parallel_rd;
reg [`WIDTH_PARADATA-1:0] parallel_rd_buf1;
reg [`WIDTH_PARADATA-1:0] para_dataout;
reg [`WIDTH_PARADATA-1:0] tr_buf;
// 当有发送命令时，锁存要发送的数据	
always@(posedge clk or negedge reset_n)
  begin
    if (!reset_n)
       tr_buf <= 8'd0;
    else if(send_cmd)
      tr_buf<=parallel_tr;
    else
      tr_buf<=tr_buf;
  end	

reg parabus_busy;
assign ackout=parabus_busy; // 
// 发送忙置位和清零电路
reg clr_busy_cmd;
always@(posedge send_cmd or posedge clr_busy_cmd)
  if(clr_busy_cmd)
	parabus_busy<=1'b0;
  else
	parabus_busy<=1'b1;

reg rd_full_reg;
reg rbus_full_trig;

assign rd_full=rd_full_reg;
// 读满标志置位和清零电路
always@(posedge rbus_full_trig or posedge rd_ack)
  begin
    if(rd_ack)
	  rd_full_reg<=1'b0;
	else
	  rd_full_reg<=1'b1;
	end
	
reg tr_flag, rd_flag;	// 发送和接受标志
reg para_dir;

parameter delay_time0 = 16'd100;
reg [15:0] delay_count0;
reg [2:0] mach_rd_next;
parameter [2:0] RD_IDLE=3'd0,
				        RD_START=3'd1,
				        RD_END=3'd2;	
// 并口接受时序电路	

reg Selctin_1;
always @(posedge clk )
  begin
      selctin_1 <= selctin;
  end
always @(posedge clk or negedge reset_n )
  begin
	if(!reset_n)
	  mach_rd_next<=RD_IDLE;
	else
	  case(mach_rd_next)
		RD_IDLE: 
		  begin
			  rd_flag<=1'b0;
			  rbus_full_trig<=1'b0;
			  para_dir<=1'b0;
			  delay_count0 <= 16'd0;
		    if((selctin_1==1'b1) & (selctin==1'b0))   // negedge of Selctin strobe
			    begin
			      para_dir<=1'b1;
			      mach_rd_next<=RD_START;
			    end	
		    else
			    begin
				    mach_rd_next<=RD_IDLE;
			    end
		  end
		RD_START: 
		  begin
		    if(selctin==1'b1)
		       mach_rd_next <= RD_IDLE;
		    else if( delay_count0 <= delay_time0)
		      begin
		        delay_count0 <= delay_count0 + 16'd1;
		        parallel_rd<=para_datain;
		        parallel_rd_buf1 <= parallel_rd;
		        if(parallel_rd !== parallel_rd_buf1)
		          begin
		            mach_rd_next <= RD_IDLE;
			        parallel_rd <= 8'd0;
			      end
		      end
		    else
		      begin
		       delay_count0 <= delay_count0;
		       mach_rd_next <= RD_END;
		      end
		  end
		RD_END: 
		  begin
			  rbus_full_trig<=1'b1;
			  delay_count0 <= 16'd0;
			  mach_rd_next<=RD_IDLE;
		  end
		default: mach_rd_next<=RD_IDLE;
	  endcase
 end

parameter delay_time1 = 16'd500;
reg [15:0] delay_count1;				
reg [2:0] mach_tr_next;
parameter [2:0] TR_IDLE=3'd0,
				        TR_START=3'd1,
				        TR_END=3'd2;
// 并口发送时序电路
always @(posedge clk or negedge reset_n )
  begin
	if(!reset_n)
	  mach_tr_next<=TR_IDLE;
	else
	  case(mach_tr_next)
		TR_IDLE: 
		  begin
			  tr_flag<=1'b0;
			  clr_busy_cmd<=1'b0;
			  delay_count1 <= 16'd0;
			  if(parabus_busy==1'b1 & para_dir==1'b0)
			    begin
			      tr_flag<=1'b1;
				  mach_tr_next<=TR_START;
			    end
			  else
			    mach_tr_next<=TR_IDLE;
		  end
		TR_START: 
		  begin
			  if(delay_count1 >= delay_time1)
			    mach_tr_next<=TR_END;
			  else
			    begin
					para_dataout<=tr_buf;
				    delay_count1 <= delay_count1 + 16'd1;
			    end				
		  end
		TR_END: 
		  begin
		      tr_flag<=1'b0;
			  clr_busy_cmd<=1'b1;
			  mach_tr_next<=TR_IDLE;
		  end	
		default: mach_tr_next<=TR_IDLE;
	  endcase
  end
 endmodule