fpga313czkz.v

windowsxp/2000下驱动程序开发软件winddriver6.0

// +FHDR----------------------------------------------------------
// Copyright (C) 2006 Casic23
// Casic23 Confidential Proprietary.
// ----------------------------------------------------------------
// FILE NAME : fpga313czkz.v
// TYPE : TOP Module
// DEPARTMENT : Casic23 team 7
// AUTHOR : jing gang
// AUTHOR EMAIL : [e-mail]
// ---------------------------------------------------------------
// Realease histroy
// VERSION DATE AUTHOR DESCRIPTION
// 		ver1.01 JAN.11 2006 Jing Gang initial version 
// ---------------------------------------------------------------
// KEYWORDS	: TLP313 
// ---------------------------------------------------------------
// PURPOSE	: scan wihich key is push down,and transmit the relative 
//            keycode to the host computer and receive the command 
//            or some code by the host computerby parallel port.  
// ---------------------------------------------------------------
// PARAMETERS
// 		 PARAM NAME		RANGE	:	DESCRIPTION	:	DEFAULT	: VA UNIT
// ---------------------------------------------------------------
// RESUSE ISSUES
//		Reset Strategy	:
//		Coclk Domain 	:
//		Critical Timing	:
//		Test Feature	:
//		Asynchronous I/F:
//		Scan Methodoly	:
//		Instantiations	:
//		Others			:
// - FHDR----------------------------------------------------------

module fpga313czkz(
	                 clk_in,
	
	                 switchin,
	                 switchen,
	
	                 lamptest,
	                 lampout,
	
	                 paradata,
	                 para_dir,
	                 //strobein,
	                 //autoin,
	                 //intin_nc,
	                 selctin,
	                 ackout
	                 //busyout,
	                 //peout,
	                 //slctout
	                 //errout_nc
	              );
	
`include        "param.v"

input clk_in;// 输入时钟
	
input [`WIDTH_SWITCHIN-1:0] switchin; // 键盘输入 
output [`WIDTH_SWITCHEN:1] switchen;// 键盘输入使能
	
input lamptest; // 灯测试输入
output [`NUM_LAMP:1] lampout; // 点灯输出
	
inout [`WIDTH_PARADATA-1:0] paradata; //并口双向数据总线
output para_dir; // 并口双向数据总线方向控制线
//input strobein; // SPP并口STROBE输入 
//input autoin; // SPP并口AUTO输入
//input intin_nc; // SPP并口init输入, 后缀_nc表示没有连接
input selctin; // SPP并口SLECT输入
output ackout; // SPP并口ACK输出
//output busyout; // SPP并口BUSY输出
//output peout; // SPP并口PE输出
//output slctout; // SPP并口SLCT输出
//output errout_nc; // SPP并口ERR输出
	
//assign errout=process_parallel_rd[0];
wire [`WIDTH_PARADATA-1:0] para_datain; // 并口模块数据输入 
wire [`WIDTH_PARADATA-1:0] para_dataout; // 并口模块数据输出
assign para_datain=paradata; // 并口模块的输入端口，直接连在双向的并口双向端口上
assign paradata=(para_dir)?8'hz:para_dataout; // 当 para_dir为“0”表示输出时，双向端口为输出端口

// generate the clk_in
// for simulate clk_1us=clk_in/40
reg [15:0] cnt1; // 分频时钟计数器
reg clk_1us; // 周期为1US时钟信号

// 时钟分频电路
always @(posedge clk_in) // clk_in=40mhz
  begin
    if(cnt1>=16'd20)
	  begin
	    cnt1<=16'd0;
		clk_1us<=~clk_1us;
	  end
	else
	  cnt1<=cnt1+16'd1;
  end	
// process_为连接不同模块端口的信号	
wire process_sw_ack;
wire process_sw_int;
wire process_reset_n;
wire [`WIDTH_KEYCODE-1:0] process_keycode;
wire process_search_start_cmd;
wire process_search_stop_cmd;
// 例化搜索模块
search_panel m1(
                     .clk(clk_1us),
			               .clk_ram(clk_1us),
			               .reset_n(process_reset_n),
			               .sw_ack(process_sw_ack),
			               .switchin(switchin),
			               .sw_int(process_sw_int),
			               .keycode(process_keycode),
			               .switch_se(switchen),
			               .search_start_cmd(process_search_start_cmd),
			               .search_stop_cmd(process_search_stop_cmd)
			              );
			
wire process_lamp_wr;
wire [`WIDTH_LAMP_DATA-1:0] process_lamp_data;
wire [`WIDTH_PARADATA-1:0] process_parallel_rd;
wire [`WIDTH_PARADATA-1:0] process_parallel_tr;
wire process_parallel_full;
wire process_parallel_ack;
wire process_parallel_send;
wire process_parallel_busy;

// 例化主处理模块
main m2(
        .clk(clk_1us),
		    .reset_n(process_reset_n),
		    .sw_code(process_keycode),
		    .sw_int(process_sw_int),
		    .sw_ack(process_sw_ack),
		    .search_start_cmd(process_search_start_cmd),
		    .search_stop_cmd(process_search_stop_cmd),
		
		    .lamp_wr(process_lamp_wr),
		    .lamp_data(process_lamp_data),
		
		    .parallel_rd(process_parallel_rd),
		    .parallel_full(process_parallel_full),
		    .parallel_ack(process_parallel_ack),
		    .parallel_tr(process_parallel_tr),
		    .parallel_send(process_parallel_send),
		    .parallel_busy(process_parallel_busy)
		   );
		
wire lamp_test; // 定义灯测试信号
assign lamp_test=lamptest; // 

wire [`NUM_LAMP:1] lamp_out; //定义灯输出信号
assign lampout=lamp_out;
// 例化点灯模块	
lamp m3(
              .clk(clk_1us),
              .lamp_wr_cmd(process_lamp_wr),
		      .reset_n(process_reset_n),
		      .lamp_test(lamp_test),
		      .lamp_in(process_lamp_data),
		      .lamp_out(lamp_out)
		    );

wire ackout; // 定义ackout信号
//wire busyout; // 定义busyout信号
//wire peout; // 定义peout信号
//wire slctout; // 定义slctout信号
// 这里为了在并口中使用ACK中断，所以将主机ACK信号不用于后面与并口通信的握手信号，而用
// 主机PE信号来代替ACK信号来使用，于是将PE信号接在后面并口通信模块的ackout端口上。由于
// 在后面的并口通信模块中，是用PE信号来作为一个发送数据的申请信号，为了实现ACK中断，所
// 以将主机的ACK信号连接到并口通信模块的peout端口上。
//wire ackout_test;
//wire peout_test;
//assign ackout=peout_test;
//assign peout=ackout_test;

//wire busyout_inv;	
//wire strobein_inv;
//wire autoin_inv;
wire selctin_inv;
// 由于通用并口信号定义，BUSY、STROBE、AUTO、SELECT、在连接器处反接，故这里反相连接保持子
// 模块paralle_port中引用的并口信号定义与通用并口寄存器中保持一致。
//assign busyout=!busyout_inv;	
//assign strobein_inv=!strobein;
//assign autoin_inv=!autoin;
assign selctin_inv=!selctin;
	
parallel_port m4(
                       .clk(clk_1us),
			                 .reset_n(process_reset_n),
			                 .rd_full(process_parallel_full),
			                 .rd_ack(process_parallel_ack),
			                 .parabus_busy(process_parallel_busy),
			                 .send_cmd(process_parallel_send),
			                 .parallel_tr(process_parallel_tr),
			                 .parallel_rd(process_parallel_rd),
			                 .para_dir(para_dir),
			                 .para_datain(para_datain),
			                 .para_dataout(para_dataout),
			               //.strobein(strobein_inv),
			               //.autoin(autoin_inv),
			               //.intin(intin_nc),
			                 .selctin(selctin_inv),
			               //  .ackout(ackout_test),
			                 .ackout(ackout)
			               //.busyout(busyout_inv),
			               //.peout(peout_test),
			               //.slctout(slctout)
			               //.errout(errout_nc)		
			               );		
	
endmodule