adsp-bf532-lqfp176.sym

ADI公司的blackfin DSP 处理器,其532/531系列实验板

pinnumber=78
T 350 2050 5 8 0 1 0 6 1
pinseq=78
T 350 2050 5 8 0 1 0 6 1
pintype=io
T 500 2000 9 8 1 1 0 0 1
pinlabel=TMR1/PPI_FS1 (Timer1/PPI Frame Sync 1)
}
P 400 2200 100 2200 1 0 1
{
T 350 2250 5 8 1 1 0 6 1
pinnumber=79
T 350 2250 5 8 0 1 0 6 1
pinseq=79
T 350 2250 5 8 0 1 0 6 1
pintype=io
T 500 2200 9 8 1 1 0 0 1
pinlabel=TMR0 (Timer 0)
}
P 400 5400 100 5400 1 0 1
{
T 350 5450 5 8 1 1 0 6 1
pinnumber=58
T 350 5450 5 8 0 1 0 6 1
pinseq=58
T 350 5450 5 8 0 1 0 6 1
pintype=out
T 500 5400 9 8 1 1 0 0 1
pinlabel=DT1SEC (Transmit Data Secondary)
}
P 400 5600 100 5600 1 0 1
{
T 350 5650 5 8 1 1 0 6 1
pinnumber=59
T 350 5650 5 8 0 1 0 6 1
pinseq=59
T 350 5650 5 8 0 1 0 6 1
pintype=out
T 500 5600 9 8 1 1 0 0 1
pinlabel=DT1PRI (Transmit Data Primary)
}
P 400 5800 100 5800 1 0 1
{
T 350 5850 5 8 1 1 0 6 1
pinnumber=60
T 350 5850 5 8 0 1 0 6 1
pinseq=60
T 350 5850 5 8 0 1 0 6 1
pintype=io
T 500 5800 9 8 1 1 0 0 1
pinlabel=TFS1 (Transmit Frame Sync)
}
P 400 6000 100 6000 1 0 1
{
T 350 6050 5 8 1 1 0 6 1
pinnumber=61
T 350 6050 5 8 0 1 0 6 1
pinseq=61
T 350 6050 5 8 0 1 0 6 1
pintype=io
T 500 6000 9 8 1 1 0 0 1
pinlabel=TSCLK1 (Transmit Serial Clock)
}
P 400 6200 100 6200 1 0 1
{
T 350 6250 5 8 1 1 0 6 1
pinnumber=62
T 350 6250 5 8 0 1 0 6 1
pinseq=62
T 350 6250 5 8 0 1 0 6 1
pintype=in
T 500 6200 9 8 1 1 0 0 1
pinlabel=DR1SEC (Receive Data Secondary)
}
P 400 6400 100 6400 1 0 1
{
T 350 6450 5 8 1 1 0 6 1
pinnumber=63
T 350 6450 5 8 0 1 0 6 1
pinseq=63
T 350 6450 5 8 0 1 0 6 1
pintype=in
T 500 6400 9 8 1 1 0 0 1
pinlabel=DR1PRI (Receive Data Primary)
}
P 400 6600 100 6600 1 0 1
{
T 350 6650 5 8 1 1 0 6 1
pinnumber=64
T 350 6650 5 8 0 1 0 6 1
pinseq=64
T 350 6650 5 8 0 1 0 6 1
pintype=io
T 500 6600 9 8 1 1 0 0 1
pinlabel=RFS1 (Receive Frame Sync)
}
P 400 6800 100 6800 1 0 1
{
T 350 6850 5 8 1 1 0 6 1
pinnumber=65
T 350 6850 5 8 0 1 0 6 1
pinseq=65
T 350 6850 5 8 0 1 0 6 1
pintype=io
T 500 6800 9 8 1 1 0 0 1
pinlabel=RSCLK1 (Receive Serial Clock)
}
P 400 3700 100 3700 1 0 1
{
T 350 3750 5 8 1 1 0 6 1
pinnumber=67
T 350 3750 5 8 0 1 0 6 1
pinseq=67
T 350 3750 5 8 0 1 0 6 1
pintype=out
T 500 3700 9 8 1 1 0 0 1
pinlabel=DT0SEC (Transmit Data Secondary)
}
P 400 3900 100 3900 1 0 1
{
T 350 3950 5 8 1 1 0 6 1
pinnumber=68
T 350 3950 5 8 0 1 0 6 1
pinseq=68
T 350 3950 5 8 0 1 0 6 1
pintype=out
T 500 3900 9 8 1 1 0 0 1
pinlabel=DT0PRI (Transmit Data Primary)
}
P 400 4100 100 4100 1 0 1
{
T 350 4150 5 8 1 1 0 6 1
pinnumber=69
T 350 4150 5 8 0 1 0 6 1
pinseq=69
T 350 4150 5 8 0 1 0 6 1
pintype=io
T 500 4100 9 8 1 1 0 0 1
pinlabel=TFS0 (Transmit Frame Sync)
}
P 400 4300 100 4300 1 0 1
{
T 350 4350 5 8 1 1 0 6 1
pinnumber=72
T 350 4350 5 8 0 1 0 6 1
pinseq=72
T 350 4350 5 8 0 1 0 6 1
pintype=io
T 500 4300 9 8 1 1 0 0 1
pinlabel=TSCLK0 (Transmit Serial Clock)
}
P 400 4500 100 4500 1 0 1
{
T 350 4550 5 8 1 1 0 6 1
pinnumber=73
T 350 4550 5 8 0 1 0 6 1
pinseq=73
T 350 4550 5 8 0 1 0 6 1
pintype=in
T 500 4500 9 8 1 1 0 0 1
pinlabel=DR0SEC (Receive Data Secondary)
}
P 400 4700 100 4700 1 0 1
{
T 350 4750 5 8 1 1 0 6 1
pinnumber=74
T 350 4750 5 8 0 1 0 6 1
pinseq=74
T 350 4750 5 8 0 1 0 6 1
pintype=in
T 500 4700 9 8 1 1 0 0 1
pinlabel=DR0PRI (Receive Data Primary)
}
P 400 4900 100 4900 1 0 1
{
T 350 4950 5 8 1 1 0 6 1
pinnumber=75
T 350 4950 5 8 0 1 0 6 1
pinseq=75
T 350 4950 5 8 0 1 0 6 1
pintype=io
T 500 4900 9 8 1 1 0 0 1
pinlabel=RFS0 (Receive Frame Sync)
}
P 400 5100 100 5100 1 0 1
{
T 350 5150 5 8 1 1 0 6 1
pinnumber=76
T 350 5150 5 8 0 1 0 6 1
pinseq=76
T 350 5150 5 8 0 1 0 6 1
pintype=io
T 500 5100 9 8 1 1 0 0 1
pinlabel=RSCLK0 (Receive Serial Clock)
}
B 400 400 12700 10500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 13100 1200 400 1200 3 0 0 0 -1 -1
L 400 1700 6800 1700 3 0 0 0 -1 -1
L 400 2400 6800 2400 3 0 0 0 -1 -1
L 400 3100 6800 3100 3 0 0 0 -1 -1
L 400 3600 6800 3600 3 0 0 0 -1 -1
L 400 5300 6800 5300 3 0 0 0 -1 -1
L 400 7000 6800 7000 3 0 0 0 -1 -1
L 400 8800 6800 8800 3 0 0 0 -1 -1
L 13100 10100 400 10100 3 0 0 0 -1 -1
L 6800 10100 6800 1200 3 0 0 0 -1 -1
L 6800 8600 13100 8600 3 0 0 0 -1 -1
L 6800 4300 13100 4300 3 0 0 0 -1 -1
L 6800 3000 13100 3000 3 0 0 0 -1 -1
L 6800 2100 13100 2100 3 0 0 0 -1 -1
T 4300 10300 9 10 1 0 0 0 2
Address bus for
Async/Sync Access
T 8100 10300 9 10 1 0 0 0 2
Data bus for
Async/Sync Access
L 6100 10900 6100 10100 3 0 0 0 -1 -1
L 8000 10900 8000 10100 3 0 0 0 -1 -1
V 350 9700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 350 9300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 350 9100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 350 8900 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 350 8600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 350 8400 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 350 8200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 350 8000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 350 7200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 350 7400 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 13150 9900 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 13150 9700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 13150 9500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 13150 8700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 13150 4100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 13150 3500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 13150 2400 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 13000 1900 13100 1975 3 0 0 0 -1 -1
L 13000 1900 13100 1825 3 0 0 0 -1 -1
L 13000 1700 13100 1775 3 0 0 0 -1 -1
L 13000 1700 13100 1625 3 0 0 0 -1 -1
L 13000 1500 13100 1575 3 0 0 0 -1 -1
L 13000 1500 13100 1425 3 0 0 0 -1 -1
L 13000 1300 13100 1375 3 0 0 0 -1 -1
L 13000 1300 13100 1225 3 0 0 0 -1 -1
L 13000 3700 13100 3775 3 0 0 0 -1 -1
L 13000 3700 13100 3625 3 0 0 0 -1 -1
L 13000 8400 13100 8475 3 0 0 0 -1 -1
L 13000 8400 13100 8325 3 0 0 0 -1 -1
L 13000 9100 13100 9175 3 0 0 0 -1 -1
L 13000 9100 13100 9025 3 0 0 0 -1 -1
L 500 2900 400 2975 3 0 0 0 -1 -1
L 500 2900 400 2825 3 0 0 0 -1 -1
V 350 7600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 12552 4527 13000 4525 3 0 0 0 -1 -1
T 4300 9300 9 10 1 0 0 0 1
Memory Interface Control
T 4100 7800 9 10 1 0 0 0 1
Asynchronous Memory Control
T 6900 9400 9 10 1 0 0 0 1
Synchronous Memory Control
T 6900 8400 9 10 1 0 0 0 1
Parallel Peripheral Interface Port / GPIO
T 6900 3600 9 10 1 0 0 0 1
JTAG Test and Emulation Port
T 6900 2500 9 10 1 0 0 0 1
Mode Controls
T 6900 1600 9 10 1 0 0 0 1
Clocks
T 5600 4200 9 10 1 0 0 0 3
Dual Channel,
Full Duplex,
Serial Port 0
T 5600 5900 9 10 1 0 0 0 3
Dual Channel,
Full Duplex,
Serial Port 1
T 5600 3300 9 10 1 0 0 0 1
IRDA / UART
T 6400 2700 9 10 1 0 0 0 1
SPI
T 6200 2000 9 10 1 0 0 0 1
Timers
T 4500 1400 9 10 1 0 0 0 1
Internal Voltage Regulator
T 6204 11004 8 10 0 0 0 0 1
numslots=0
L 6937 6687 9229 6687 3 0 0 0 -1 -1
L 9229 6687 9229 7520 3 0 0 0 -1 -1
L 9229 7520 6937 7520 3 0 0 0 -1 -1
L 6937 7520 6937 6687 3 0 0 0 -1 -1
L 8192 7137 8192 7421 3 0 0 0 -1 -1
L 8192 7421 8135 7421 3 0 0 0 -1 -1
L 8135 7421 8135 7232 3 0 0 0 -1 -1
L 8135 7232 8015 7421 3 0 0 0 -1 -1
L 8015 7421 7957 7421 3 0 0 0 -1 -1
L 7957 7421 7957 7137 3 0 0 0 -1 -1
L 7957 7137 8014 7137 3 0 0 0 -1 -1
L 8014 7137 8014 7328 3 0 0 0 -1 -1
L 8014 7328 8139 7137 3 0 0 0 -1 -1
L 8139 7137 8192 7137 3 0 0 0 -1 -1
L 8662 7137 8662 7185 3 0 0 0 -1 -1
L 8662 7185 8534 7185 3 0 0 0 -1 -1
L 8534 7185 8534 7421 3 0 0 0 -1 -1
L 8534 7421 8478 7421 3 0 0 0 -1 -1
L 8478 7421 8478 7137 3 0 0 0 -1 -1
L 8478 7137 8662 7137 3 0 0 0 -1 -1
L 8466 7137 8359 7421 3 0 0 0 -1 -1
L 8359 7421 8301 7421 3 0 0 0 -1 -1
L 8301 7421 8205 7137 3 0 0 0 -1 -1
L 8205 7137 8262 7137 3 0 0 0 -1 -1
L 8262 7137 8281 7200 3 0 0 0 -1 -1
L 8281 7200 8386 7200 3 0 0 0 -1 -1
L 8386 7200 8408 7137 3 0 0 0 -1 -1
L 8408 7137 8466 7137 3 0 0 0 -1 -1
L 8368 7240 8367 7240 3 0 0 0 -1 -1
L 8367 7240 8295 7240 3 0 0 0 -1 -1
L 8295 7240 8295 7255 3 0 0 0 -1 -1
L 8295 7255 8331 7362 3 0 0 0 -1 -1
L 8331 7362 8367 7255 3 0 0 0 -1 -1
L 8367 7255 8368 7249 3 0 0 0 -1 -1
L 8368 7249 8368 7239 3 0 0 0 -1 -1
L 8368 7239 8368 7240 3 0 0 0 -1 -1
L 7946 7136 7838 7420 3 0 0 0 -1 -1
L 7838 7420 7780 7420 3 0 0 0 -1 -1
L 7780 7420 7685 7136 3 0 0 0 -1 -1
L 7685 7136 7742 7136 3 0 0 0 -1 -1
L 7742 7136 7761 7199 3 0 0 0 -1 -1
L 7761 7199 7866 7199 3 0 0 0 -1 -1
L 7866 7199 7888 7136 3 0 0 0 -1 -1
L 7888 7136 7946 7136 3 0 0 0 -1 -1
L 7846 7239 7776 7239 3 0 0 0 -1 -1
L 7776 7239 7778 7257 3 0 0 0 -1 -1
L 7778 7257 7810 7361 3 0 0 0 -1 -1
L 7810 7361 7846 7256 3 0 0 0 -1 -1
L 7846 7256 7847 7238 3 0 0 0 -1 -1
L 7847 7238 7846 7239 3 0 0 0 -1 -1
L 8795 7424 8737 7411 3 0 0 0 -1 -1
L 8737 7411 8694 7378 3 0 0 0 -1 -1
L 8694 7378 8668 7331 3 0 0 0 -1 -1
L 8668 7331 8659 7278 3 0 0 0 -1 -1
L 8659 7278 8667 7224 3 0 0 0 -1 -1
L 8667 7224 8692 7176 3 0 0 0 -1 -1
L 8692 7176 8734 7143 3 0 0 0 -1 -1
L 8734 7143 8794 7130 3 0 0 0 -1 -1
L 8794 7130 8852 7143 3 0 0 0 -1 -1
L 8852 7143 8893 7176 3 0 0 0 -1 -1
L 8893 7176 8918 7223 3 0 0 0 -1 -1
L 8918 7223 8926 7277 3 0 0 0 -1 -1
L 8926 7277 8917 7331 3 0 0 0 -1 -1
L 8917 7331 8893 7378 3 0 0 0 -1 -1
L 8893 7378 8852 7411 3 0 0 0 -1 -1
L 8852 7411 8795 7424 3 0 0 0 -1 -1
L 8794 7376 8828 7367 3 0 0 0 -1 -1
L 8828 7367 8852 7345 3 0 0 0 -1 -1
L 8852 7345 8866 7313 3 0 0 0 -1 -1
L 8866 7313 8871 7277 3 0 0 0 -1 -1
L 8871 7277 8866 7241 3 0 0 0 -1 -1
L 8866 7241 8851 7209 3 0 0 0 -1 -1
L 8851 7209 8826 7187 3 0 0 0 -1 -1
L 8826 7187 8791 7179 3 0 0 0 -1 -1
L 8791 7179 8757 7187 3 0 0 0 -1 -1
L 8757 7187 8733 7210 3 0 0 0 -1 -1
L 8733 7210 8719 7242 3 0 0 0 -1 -1
L 8719 7242 8715 7278 3 0 0 0 -1 -1
L 8715 7278 8720 7315 3 0 0 0 -1 -1
L 8720 7315 8735 7346 3 0 0 0 -1 -1
L 8735 7346 8759 7369 3 0 0 0 -1 -1
L 8759 7369 8793 7377 3 0 0 0 -1 -1
L 8793 7377 8794 7376 3 0 0 0 -1 -1
L 9200 7143 9200 7287 3 0 0 0 -1 -1
L 9200 7287 9083 7287 3 0 0 0 -1 -1
L 9083 7287 9083 7243 3 0 0 0 -1 -1
L 9083 7243 9151 7243 3 0 0 0 -1 -1
L 9151 7243 9151 7229 3 0 0 0 -1 -1
L 9151 7229 9146 7220 3 0 0 0 -1 -1
L 9146 7220 9132 7202 3 0 0 0 -1 -1
L 9132 7202 9109 7185 3 0 0 0 -1 -1
L 9109 7185 9076 7177 3 0 0 0 -1 -1
L 9076 7177 9039 7186 3 0 0 0 -1 -1
L 9039 7186 9014 7210 3 0 0 0 -1 -1
L 9014 7210 8999 7242 3 0 0 0 -1 -1
L 8999 7242 8994 7279 3 0 0 0 -1 -1
L 8994 7279 9000 7316 3 0 0 0 -1 -1
L 9000 7316 9016 7348 3 0 0 0 -1 -1
L 9016 7348 9041 7370 3 0 0 0 -1 -1
L 9041 7370 9077 7378 3 0 0 0 -1 -1
L 9077 7378 9103 7373 3 0 0 0 -1 -1
L 9103 7373 9122 7361 3 0 0 0 -1 -1
L 9122 7361 9135 7345 3 0 0 0 -1 -1
L 9135 7345 9144 7330 3 0 0 0 -1 -1
L 9144 7330 9193 7331 3 0 0 0 -1 -1
L 9193 7331 9189 7347 3 0 0 0 -1 -1
L 9189 7347 9173 7377 3 0 0 0 -1 -1
L 9173 7377 9159 7393 3 0 0 0 -1 -1
L 9159 7393 9137 7408 3 0 0 0 -1 -1
L 9137 7408 9110 7420 3 0 0 0 -1 -1
L 9110 7420 9078 7424 3 0 0 0 -1 -1
L 9078 7424 9018 7411 3 0 0 0 -1 -1
L 9018 7411 8976 7378 3 0 0 0 -1 -1
L 8976 7378 8950 7332 3 0 0 0 -1 -1
L 8950 7332 8941 7279 3 0 0 0 -1 -1
L 8941 7279 8949 7226 3 0 0 0 -1 -1
L 8949 7226 8973 7179 3 0 0 0 -1 -1
L 8973 7179 9014 7146 3 0 0 0 -1 -1
L 9014 7146 9071 7132 3 0 0 0 -1 -1
L 9071 7132 9105 7136 3 0 0 0 -1 -1
L 9105 7136 9130 7149 3 0 0 0 -1 -1
L 9130 7149 9147 7162 3 0 0 0 -1 -1
L 9147 7162 9156 7171 3 0 0 0 -1 -1
L 9156 7171 9155 7143 3 0 0 0 -1 -1
L 9155 7143 9200 7143 3 0 0 0 -1 -1
L 7577 6781 7577 7419 3 0 0 0 -1 -1
L 7577 7419 6943 7419 3 0 0 0 -1 -1
L 6943 7419 6943 6781 3 0 0 0 -1 -1
L 6943 6781 7577 6781 3 0 0 0 -1 -1
L 7471 7096 7074 6862 3 0 0 0 -1 -1
L 7074 6862 7074 7320 3 0 0 0 -1 -1
L 7074 7320 7471 7096 3 0 0 0 -1 -1
L 8408 7056 8408 7071 3 0 0 0 -1 -1
L 8408 7071 8352 7071 3 0 0 0 -1 -1
L 8352 7071 8290 6864 3 0 0 0 -1 -1
L 8290 6864 8226 7072 3 0 0 0 -1 -1
L 8226 7072 8169 7072 3 0 0 0 -1 -1
L 8169 7072 8169 7057 3 0 0 0 -1 -1
L 8169 7057 8263 6789 3 0 0 0 -1 -1
L 8263 6789 8317 6789 3 0 0 0 -1 -1
L 8317 6789 8408 7056 3 0 0 0 -1 -1
L 8980 6788 8980 6836 3 0 0 0 -1 -1
L 8980 6836 8827 6836 3 0 0 0 -1 -1
L 8827 6836 8827 6911 3 0 0 0 -1 -1
L 8827 6911 8957 6911 3 0 0 0 -1 -1
L 8957 6911 8957 6962 3 0 0 0 -1 -1
L 8957 6962 8826 6962 3 0 0 0 -1 -1
L 8826 6962 8826 7021 3 0 0 0 -1 -1
L 8826 7021 8973 7021 3 0 0 0 -1 -1
L 8973 7021 8973 7072 3 0 0 0 -1 -1
L 8973 7072 8771 7072 3 0 0 0 -1 -1
L 8771 7072 8771 6788 3 0 0 0 -1 -1
L 8771 6788 8980 6788 3 0 0 0 -1 -1
L 8156 6788 8156 6836 3 0 0 0 -1 -1
L 8156 6836 8000 6836 3 0 0 0 -1 -1
L 8000 6836 8000 6913 3 0 0 0 -1 -1
L 8000 6913 8133 6913 3 0 0 0 -1 -1
L 8133 6913 8133 6964 3 0 0 0 -1 -1
L 8133 6964 7999 6964 3 0 0 0 -1 -1
L 7999 6964 7999 7025 3 0 0 0 -1 -1
L 7999 7025 8151 7025 3 0 0 0 -1 -1
L 8151 7025 8151 7072 3 0 0 0 -1 -1
L 8151 7072 7942 7072 3 0 0 0 -1 -1
L 7942 7072 7942 6788 3 0 0 0 -1 -1
L 7942 6788 8156 6788 3 0 0 0 -1 -1
L 7921 6926 7912 6983 3 0 0 0 -1 -1
L 7912 6983 7887 7030 3 0 0 0 -1 -1
L 7887 7030 7846 7061 3 0 0 0 -1 -1
L 7846 7061 7791 7072 3 0 0 0 -1 -1
L 7791 7072 7681 7072 3 0 0 0 -1 -1
L 7681 7072 7681 6788 3 0 0 0 -1 -1
L 7681 6788 7790 6788 3 0 0 0 -1 -1
L 7790 6788 7848 6798 3 0 0 0 -1 -1
L 7848 6798 7889 6826 3 0 0 0 -1 -1
L 7889 6826 7913 6869 3 0 0 0 -1 -1
L 7913 6869 7921 6925 3 0 0 0 -1 -1
L 7921 6925 7921 6926 3 0 0 0 -1 -1
L 7862 6927 7859 6895 3 0 0 0 -1 -1
L 7859 6895 7849 6865 3 0 0 0 -1 -1
L 7849 6865 7827 6842 3 0 0 0 -1 -1
L 7827 6842 7789 6832 3 0 0 0 -1 -1
L 7789 6832 7741 6831 3 0 0 0 -1 -1
L 7741 6831 7741 7023 3 0 0 0 -1 -1
L 7741 7023 7785 7023 3 0 0 0 -1 -1
L 7785 7023 7823 7013 3 0 0 0 -1 -1
L 7823 7013 7846 6988 3 0 0 0 -1 -1
L 7846 6988 7858 6957 3 0 0 0 -1 -1
L 7858 6957 7861 6928 3 0 0 0 -1 -1
L 7861 6928 7862 6927 3 0 0 0 -1 -1
L 8485 6789 8485 7071 3 0 0 0 -1 -1
L 8485 7071 8425 7071 3 0 0 0 -1 -1
L 8425 7071 8425 6789 3 0 0 0 -1 -1
L 8425 6789 8485 6789 3 0 0 0 -1 -1
L 8761 6880 8705 6880 3 0 0 0 -1 -1
L 8705 6880 8701 6869 3 0 0 0 -1 -1
L 8701 6869 8691 6851 3 0 0 0 -1 -1
L 8691 6851 8673 6833 3 0 0 0 -1 -1
L 8673 6833 8643 6826 3 0 0 0 -1 -1
L 8643 6826 8610 6835 3 0 0 0 -1 -1
L 8610 6835 8587 6859 3 0 0 0 -1 -1
L 8587 6859 8572 6893 3 0 0 0 -1 -1
L 8572 6893 8568 6931 3 0 0 0 -1 -1
L 8568 6931 8572 6969 3 0 0 0 -1 -1
L 8572 6969 8587 7002 3 0 0 0 -1 -1
L 8587 7002 8610 7024 3 0 0 0 -1 -1
L 8610 7024 8643 7031 3 0 0 0 -1 -1
L 8643 7031 8663 7025 3 0 0 0 -1 -1
L 8663 7025 8681 7011 3 0 0 0 -1 -1
L 8681 7011 8694 6994 3 0 0 0 -1 -1
L 8694 6994 8704 6978 3 0 0 0 -1 -1
L 8704 6978 8760 6978 3 0 0 0 -1 -1
L 8760 6978 8758 6986 3 0 0 0 -1 -1
L 8758 6986 8753 6999 3 0 0 0 -1 -1
L 8753 6999 8746 7014 3 0 0 0 -1 -1
L 8746 7014 8735 7031 3 0 0 0 -1 -1
L 8735 7031 8719 7048 3 0 0 0 -1 -1
L 8719 7048 8698 7062 3 0 0 0 -1 -1
L 8698 7062 8671 7072 3 0 0 0 -1 -1
L 8671 7072 8637 7076 3 0 0 0 -1 -1
L 8637 7076 8578 7063 3 0 0 0 -1 -1
L 8578 7063 8537 7030 3 0 0 0 -1 -1
L 8537 7030 8515 6982 3 0 0 0 -1 -1
L 8515 6982 8509 6928 3 0 0 0 -1 -1
L 8509 6928 8519 6873 3 0 0 0 -1 -1
L 8519 6873 8545 6826 3 0 0 0 -1 -1
L 8545 6826 8584 6793 3 0 0 0 -1 -1
L 8584 6793 8636 6781 3 0 0 0 -1 -1
L 8636 6781 8675 6786 3 0 0 0 -1 -1
L 8675 6786 8705 6797 3 0 0 0 -1 -1
L 8705 6797 8727 6813 3 0 0 0 -1 -1
L 8727 6813 8742 6831 3 0 0 0 -1 -1
L 8742 6831 8752 6849 3 0 0 0 -1 -1
L 8752 6849 8757 6864 3 0 0 0 -1 -1
L 8757 6864 8759 6875 3 0 0 0 -1 -1
L 8759 6875 8760 6880 3 0 0 0 -1 -1
L 8760 6880 8761 6880 3 0 0 0 -1 -1
L 9212 6869 9206 6905 3 0 0 0 -1 -1
L 9206 6905 9188 6929 3 0 0 0 -1 -1
L 9188 6929 9159 6945 3 0 0 0 -1 -1
L 9159 6945 9118 6955 3 0 0 0 -1 -1
L 9118 6955 9090 6960 3 0 0 0 -1 -1
L 9090 6960 9065 6967 3 0 0 0 -1 -1
L 9065 6967 9048 6979 3 0 0 0 -1 -1
L 9048 6979 9041 6999 3 0 0 0 -1 -1
L 9041 6999 9047 7015 3 0 0 0 -1 -1
L 9047 7015 9061 7025 3 0 0 0 -1 -1
L 9061 7025 9079 7030 3 0 0 0 -1 -1
L 9079 7030 9098 7032 3 0 0 0 -1 -1
L 9098 7032 9124 7027 3 0 0 0 -1 -1
L 9124 7027 9139 7016 3 0 0 0 -1 -1
L 9139 7016 9146 7003 3 0 0 0 -1 -1
L 9146 7003 9149 6993 3 0 0 0 -1 -1
L 9149 6993 9202 6992 3 0 0 0 -1 -1
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author=Ivan Danov
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email=[e-mail]
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dist-license=GPL
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