syslib.c

mtx604在vxworks下的bsp源代码

/* sysLib.c - Motorola MTXPlus board series system-dependent library */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01c,29apr02,sbs  Removing compiler warnings.
01b,26mar02,dtr  Removing compiler warnings.
01a,04jun99,dmw  Created from sysLib.c, 02k,20apr99,srr.
*/

/*
DESCRIPTION
This library provides board-specific routines.	The chip drivers included are:

    i8250Sio.c		- Intel 8250 UART driver
    ppcDecTimer.c	- PowerPC decrementer timer library (system clock)
    ravenAuxClk.c	- Motorola Raven timer driver for auxiliary clock.
    ravenMpic.c		- raven Mpic / W83C553 PIB/IBC Interrupt Controller
    ravenPci.c		- Raven PCI Bus bridge chip initialization
    pciAutoConfigLib.c	- PCI device auto-configuration library
    pciConfigLib.c	- PCI Configuration Space Access Library
    pciConfigShow.c	- Show routines of PCI bus library.
    dec21x40End.o	- 10baseT/100baseTX DEC 21x4x Ethernet driver
    byteNvRam.c 	- byte-oriented generic non-volatile RAM library
    ns8730xSuperIo.c	- Super I/O chip initialization
    ataDrv.o		- ATA/EIDE interface driver
    isaDma.c		- I8237 ISA DMA transfer interface library
    fdcDrv.c		- driver for PS2 floppy device controller(FDC)
    hawkI2c.c 		- Falcon/Hawk I2C support.

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "pci.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "drv/end/dec21x40End.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"

#include "drv/pci/pciConfigLib.h"

#ifdef INCLUDE_FD
#   include "fdcDrv.c"	/* include floppy disk driver */
#   include "isaDma.c"   /* include DMA driver */
#endif

/* defines */

#define ZERO	0


/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers can be disabled if the VS and VP bits are both clear
 * in the upper BAT register of each pair.  In the default configuration
 * (coded below) the VS and VP bits are cleared and thus the BAT registers
 * are disabled.  To enable the BAT registers, change the construct coded
 * below the upper BAT register:
 *
 *	      & ~(_MMU_UBAT_VS | _MMU_UBAT_VP)),
 *	      which clears VS and VP
 *				to
 *	      | (_MMU_UBAT_VS | _MMU_UBAT_VP)),
 *	      which sets VS and VP
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */

    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | (_MMU_UBAT_BL_1M &
    ~(_MMU_UBAT_VS & _MMU_UBAT_VP))),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */

    0, 0,

    /* D BAT 1 */

    0, 0,

    /* D BAT 2 */

    0, 0,

    /* D BAT 3 */

    0, 0
    };


/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 * *** EXTENDED_VME configuration ***
 *
 * The user can use TLBs, and/or BATs, to map VME A32 space to the processor.
 * The default is to use TLBs (MMU).  Change the table entry below to use
 * a different method. (See "MODIFY A32 VME WINDOW HERE")
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    {
    /* Local DRAM - Must be second entry in sysPhysMemDesc for Auto Sizing */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* Access to PCI ISA I/O space */

    {
    (void *) ISA_MSTR_IO_LOCAL,
    (void *) ISA_MSTR_IO_LOCAL,
    ISA_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI I/O space */

    {
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI memory space */

    {
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI IO memory space */

    {
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    /* MPIC Regs */

    (void *) MPIC_BASE_ADRS,
    (void *) MPIC_BASE_ADRS,
    MPIC_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) FALCON_BASE_ADRS,
    (void *) FALCON_BASE_ADRS,
    FALCON_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) RAVEN_BASE_ADRS,
    (void *) RAVEN_BASE_ADRS,
    RAVEN_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) FLASH_BASE_ADRS,
    (void *) FLASH_BASE_ADRS,
    FLASH_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    }
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int   sysBus      = VME_BUS;            /* system bus type */
int   sysCpu      = CPU;                /* system CPU type (MC680x0) */
char * sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int   sysProcNum;			/* processor number of this CPU */
int   sysFlags;				/* boot flags */
char  sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char  sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
UINT  sysVectorIRQ0  = INT_VEC_IRQ0;	/* vector for IRQ0 */
LOCAL int   sysRavPciBusNo;		/* Raven Config Space BDF address */
LOCAL int   sysRavPciDevNo;
LOCAL int   sysRavPciFuncNo;

/* last 5 nibbles are board specific, initialized in sysHwInit */

unsigned char lnEnetAddr [6] = { 0x08, 0x00, 0x3e, 0x00, 0x00, 0x00 };
unsigned char clearWd [1]  = { 0x00 };

#ifdef	INCLUDE_ATA

ATA_RESOURCE    ataResources[ATA_MAX_CTRLS];

/* 
 * The first member in the ATA_TYPE struct has a dual purpose.
 *   1) If cylinders == 0, the device location is not probed at startup.
 *   2) If cylinders |= 0, the device location is probed, and if a device
 *      is found, the driver will fill in the first 3 member of the struct
 *      with number of cylinders, number of heads, and sectors per track.
 *
 * The last 2 members of the struct are static and should not be changed.
 *
 * The ATA_TYPE struct has the following layout:
 *   int cylinders;
 *   int heads;
 *   int sectorsTrack;
 *   int bytesSector;
 *   int precomp;
 *
 * NOTE: If configType == ATA_GEO_FORCE, the user needs to fill in
 * values for cylinders, heads, and sectorsTrack.
 */

ATA_TYPE        ataTypes [ATA_MAX_CTRLS][ATA_MAX_DRIVES] =
    {
	{
	{ATA_DEV0_STATE, 0, 0, 512, 0xff},  /* controller 0, drive 0 */
	{ATA_DEV1_STATE, 0, 0, 512, 0xff},  /* controller 0, drive 1 */
    	},
        {
	{ATA_DEV2_STATE, 0, 0, 512, 0xff},  /* controller 1, drive 0 */
	{ATA_DEV3_STATE, 0, 0, 512, 0xff},  /* controller 1, drive 1 */
    	}
    };
#endif	/* INCLUDE_ATA */

/* locals */

LOCAL char sysModelStr[80];
LOCAL char sysWrongCpuMsg[] = WRONG_CPU_MSG;
UINT32 sysProbeFault = 0; /* used by dsi exception trap handler */


/* forward declarations */

void	sysDebugMsg (char * str, UINT32 recovery);
void	sysSpuriousIntHandler (void);
void	sysCpuCheck (void);
char *	sysPhysMemTop (void);
void	sysDec21x40UpdateLoadStr (void);
UCHAR	sysNvRead (ULONG);
void	sysNvWrite (ULONG,UCHAR);
void	sysBusTasClear (volatile char * address);
STATUS	sysBusProbe (char *, int, int, char *);
void	sysMsDelay (UINT);
void	sysDelay (void);
void	sysPciInsertLong (UINT32, UINT32, UINT32);
void	sysPciInsertWord (UINT32, UINT16, UINT16);
void	sysPciInsertByte (UINT32, UINT8, UINT8);
void	sysPciOutLongConfirm (UINT32, UINT32);
void	sysPciOutWordConfirm (UINT32, UINT16);
void	sysPciOutByteConfirm (UINT32, UINT8);

/* externals */

IMPORT UCHAR  sysInByte (ULONG);
IMPORT void   sysOutByte (ULONG, UCHAR);
IMPORT UINT16 sysIn16 (UINT16 *);
IMPORT void   sysOut16 (UINT16 *, UINT16);
IMPORT UINT32 sysIn32 (UINT32 *);
IMPORT void   sysOut32 (UINT32 *, UINT32);
IMPORT void   sysPciRead32 (UINT32, UINT32 *);
IMPORT void   sysPciWrite32 (UINT32, UINT32);
IMPORT void   sysClkIntCIO (void);
IMPORT STATUS sysMemProbeSup (int length, char * src, char * dest);
IMPORT int    sysProbeExc ();
IMPORT void   sysClkIntCIO (void);
IMPORT UINT   sysGetBusSpd (void);

IMPORT void 		usrRoot (char *pMemPoolStart, unsigned memPoolSize);
IMPORT char	end [];			/* defined by the loader */
/* BSP DRIVERS */

#include "pci/pciAutoConfigLib.c"
#include "pci/pciConfigLib.c"		/* PCI config space access */
#include "./sysBusPci.c"

#ifdef INCLUDE_SHOW_ROUTINES
#   include "pci/pciConfigShow.c"	/* display of PCI config space */
#endif
#include "./sysEnd.c"
#include "sysSerial.c"
#include "mem/byteNvRam.c"
#include "timer/ppcDecTimer.c"		/* PPC603 & 604 have on chip timers */
#include "sysScsi.c"			/* sysScsiInit routine */
#ifdef	INCLUDE_ATA
#   include "sysAta.c"			/* sysAtaInit routine */
#endif	/* INCLUDE_ATA */
#include "sysCache.c"
#include "ns8730xSuperIo.c"
#include "ravenPci.c"
#ifdef INCLUDE_MPIC
#   include "ravenMpic.c"
#else
#   include "sl82565IntrCtl.c"
#endif /* INCLUDE_MPIC */
#include "timer/ppcZ8536Timer.c"
#ifdef INCLUDE_RAVEN_AUXCLK
#  include "ravenAuxClk.c"
#endif  /* INCLUDE_RAVEN_AUXCLK */

/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.  The returned string
* depends on the board model and CPU version being used, for example,
* "Motorola MTX - MPC 604e".
*
* RETURNS: A pointer to the string.
*/

char * sysModel (void)
    {
    char   base_type;
    char * pBrdType;
    int    cpu;

    /* Determine board type */

    base_type = *SYS_REG_BMSR;
    switch (base_type)
        {
        case SYS_REG_BMSR_MTX:
        case SYS_REG_BMSR_MTX_PP:
                pBrdType = "MTX";
                break;
        case SYS_REG_BMSR_MTX_PLUS:
                pBrdType = "MTXPlus";
                break;
        default:
                pBrdType = "Unknown";
                break;
        }

    /* Determine CPU type and build display string */

    cpu = CPU_TYPE;
    switch (cpu)
	{
	case CPU_TYPE_604E:
	    sprintf (sysModelStr, "Motorola %s - MPC 604e", pBrdType);
	    break;
        case CPU_TYPE_604R:
            sprintf (sysModelStr, "Motorola %s - MPC 604r", pBrdType);
            break;
	case CPU_TYPE_603P:
	    sprintf (sysModelStr, "Motorola %s - MPC 603p", pBrdType);
	    break;
	case CPU_TYPE_603E:
	    sprintf (sysModelStr, "Motorola %s - MPC 603e", pBrdType);
	    break;
        case CPU_TYPE_750:
	    sprintf (sysModelStr, "Motorola %s - MPC 750", pBrdType);
	    break;
	default:
	    sprintf (sysModelStr, "Motorola %s - MPC 60%d", pBrdType, cpu);
	    break;
	}

    return (sysModelStr);
    }