rominit.s

mtx603在vxworks下的bsp模板源代码

	rlwinm	r9,r13,8,8,31		/* extract PowerPC A0-A7 bits */
	stbx	r9,r7,r5		/* write DRAM bank base-address reg */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	lbzx	r9,r7,r4		/* read DRAM attributes register */
	ori	r9,r9,0x80		/* set bank enable bit */
	stbx	r9,r7,r4		/* write DRAM attributes register */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	lwz	r9,DRAM_SIZE1(r10)	/* load DRAM size for this entry */
	add	r25,r25,r9		/* add to the total DRAM size */
	add	r13,r13,r9		/* add it to the memory base address */

.falcon_i_sz_no:
	addi	r7,r7,1			/* increment bank index */
	cmpli	0,0,r7,NBANKS		/* are we done yet? */
	bc	4,2,.falcon_i_sz_b	/* if not equal, no, branch */

	addi	r10,r10,8		/* increment to next table entry */
	lwz	r14,0(r10)		/* load memory size variable */
	cmpl	0,0,r14,r23		/* check for table end */
	bc	4,2,.falcon_i_sz	/* if not equal, no, branch */

	/* work-around for a scrubber/refresh logic bug */

	lwz	r4,0x10(r22)		/* copy the bank enables/sizes reg */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	addis	r5,r0,0			/* gimme a zero */
	stw	r5,0x10(r22)		/* disable all, set sizes to zero */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	stw	r5,0x48(r22)		/* clr ROW/COL addr of refresh/scrub */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	stw	r4,0x10(r22)		/* restore the bank enables/sizes reg */
	eieio				/* data synchronize */
	sync				/* data synchronize */


#ifdef INCLUDE_I2C
/*  Re-program the DRAM control bits to their final (working) state.  */

	stwu    sp, -40(sp)		/* create an ABI stack frame */

	bl	sysDramSpdGet		/* get RAM spd0/1 bits in r3 */
	or	r18,r3,r3		/* move r3 to r4 */

	bl	sysDimmRefreshRateGet	/* get refresh rate in r3 */
	cmpli   cr0, 0, r3, 0		/* Normal refresh rate (0) ? */
	beq	falcon_i_1		/* branch if yes */

	ori	r3,r3,SYS_REG_GCR_FREF	/* Setup for fast refresh rate */

falcon_i_1:
	bl	sysHawkDimmTypeGet	/* get DIMM Config Type (ECC) in r3 */
	or	r5,r3,r3		/* move r3 to r5 */

	addi	sp, sp, 40		/* remove ABI stack frame */

	or	r18,r3,r18		/* ISA_HOLE=0, ADIS=0, ... */
	stw	r18,0x08(r22)		/* Update Falcon's general cntrl reg */
	eieio				/* synchronize the data stream */
	sync				/* synchronize the data stream */

	cmpli	0,0,r5,DIMM_ECC_TYPE	/* skip if not ECC type */
	bc	4,2,endFalconInit
#endif  /* INCLUDE_I2C */

#ifdef	INCLUDE_ECC
	/*
	 *	The purpose of this section is to enable the ECC of the
	 *	DRAM.  To do this, it is first necessary to initialize the
	 *	ECC check bits.  The ECC check bits are initialized by
	 *	initializing all of DRAM.
	 *
	 *	input:
	 *		r25	= Total DRAM size (in bytes)
	 *	notes:
	 *		1. must run as a supervisor function
	 *		2. interrupts must be masked
	 *		3. address translation (MMU) disabled
	 *		4. assumes ECC Control register is in a power-up state
	 *		5. The scrubber is not enabled (SWEN=0).  This provides
	 *		   better performance at the expense of less fault
	 *		   tolerance.
	 */

.falconScrub:

	/* setup local variables */

	addi	r15,r0,0		/* load starting addr - always zero */
	or	r16,r25,r25		/* load number of bytes		    */
	rlwinm	r16,r16,29,3,31		/* calculate number of doubles      */

	/* Make sure FPU is enabled; it's needed for DRAM loads and stores */

	mfmsr	r14			/* Save current value of MSR in r14 */
	addi	r4,r0,0x2000		/* FP bit definition */
	or	r4,r4,r14
	mtmsr	r4
	isync

	/*
	 * invalidate/enable the processor data cache, one of the assumptions
	 * is that address translation is disabled, the default caching mode
	 * is copy-back when address translation is disabled, copy-back mode
	 * is the recommended caching mode
	 */

	stwu	sp, -64(sp)		/* Create an ABI stack frame */
	bl	dCacheInval
	bl	dCacheOn
	addi	sp,sp,64		/* Remove ABI stack frame */

	/*
	 * Loop through the entire DRAM array and initialize memory.  This has
	 * the side effect of initializing the ECC check bits because they are
	 * always updated when the DRAM is written.
	 *
	 * The data path to DRAM is the size of a cache line (128-bits), this
	 * is why the data cache is enabled, the initialization of the ECC
	 * check bits are optimized when a cache line write/flush occurs
	 */

falconScrubStart:
	addi	r17,r15,-8		/* starting address - munged */
	mtspr	9,r16			/* load number of doubles in counter */
falconScrubIloop:
	lfdu	0,8(r17)
	stfd	0,0(r17)
	bc	16,0,falconScrubIloop	/* branch till counter == 0 */
	eieio
	sync

	/*
	 * Loop through the entire DRAM array again.
	 * Looping through the entire DRAM array is not necessary just
	 * convenient.  What is necessary is flushing the data cache from
	 * the previous loop so that the last segment (data cache size) of
	 * DRAM is initialized.
	 */

	addi	r17,r15,-8		/* starting address - munged */
	mtspr	9,r16			/* load number of doubles in counter */
falconScrubFloop:
	lfdu	0,8(r17)
	bc	16,0,falconScrubFloop	/* branch till counter == 0 */

	eieio
	sync

	/* disable the data cache */

	stwu	sp, -64(sp)		/* Create an ABI stack frame */
	bl	dCacheInval
	bl	dCacheOff
	addi	sp,sp,64		/* Remove ABI stack frame */

	/* Restore original value of MSR before FPU was forced on */

	mtmsr	r14
	isync

	/* Clear any possible error conditions that occurred during init */

	lis	r14, HI(FALCON_BASE_ADRS)
	ori	r14, r14, LO(FALCON_BASE_ADRS)

	addis	r9,r0,0x8000		/* ELOG=1,ESEN=0,SCOF=1 */
	ori	r9,r9,0x0100
	stw	r9,0x30(r14)		/* Update Error Logger register */
	eieio
	sync

	/*
	 * Enable ECC and assert Machine Check pin on multiple-bit
	 * error detection
	 */

	addis	r9,r0,0x0000		/* RWCB=0,DERC=0,xIEN=0,MCKEN=1 */
	ori	r9,r9,0x0001
	stw	r9,0x28(r14)		/* Update ECC Control register */
	eieio
	sync

	/* Set Enable Machine Check Enable Pin (EMCP) bit in HID0 */

	addis	r9,r0,0x8000
	ori	r9,r9,0x0000
        mfspr   r4,HID0
	or	r4,r4,r9
        mtspr   HID0,r4 

#endif	/* INCLUDE_ECC */

/* End of Falcon Init */

endFalconInit:
        /*
         * Disable sequential instruction execution (go superscalar) and 
         * enable branch history table for the 604
         */

        mfspr   r3,HID0
        ori     r3,r3,(_PPC_HID0_SIED | _PPC_HID0_BHTE )
        mtspr   HID0,r3

#if	FALSE				/* XXX TPR SDA not supported yet */
        /* initialize r2 and r13 according to EABI standard */

	lis     r2, HI(_SDA2_BASE_)
	ori	r2, r2, LO(_SDA2_BASE_)
	lis     r13, HI(_SDA_BASE_)
	ori	r13, r13, LO(_SDA_BASE_)
#endif

	/* go to C entry point */

	or	r3, r24, r24		/* Restore startType */
	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */

        lis     r6, HI(romStart)
        ori	r6, r6, LO(romStart)

        lis     r7, HI(romInit)
        ori	r7, r7, LO(romInit)

        lis     r8, HI(ROM_TEXT_ADRS)
        ori	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7
	add	r6, r6, r8 

	mtlr	r6
	blr


#ifdef	INCLUDE_ECC
/******************************************************************************
*
* dCacheOn - Turn Data Cache On
*
* void dCacheOn (void)
*/

_dCacheOn:
dCacheOn:
	/* Get cpu type */

	mfspr	r3,PVR
	rlwinm	r3,r3,16,16,31

	cmpli	0,0,r3,CPU_TYPE_603
	bc	12,2,dCacheOn603
	cmpli	0,0,r3,CPU_TYPE_604
	bc	12,2,dCacheOn604
	cmpli	0,0,r3,CPU_TYPE_603E
	bc	12,2,dCacheOn603
        cmpli   0,0,r3,CPU_TYPE_603P
        bc      12,2,dCacheOn603
        cmpli   0,0,r3,CPU_TYPE_750
        bc	12,2,dCacheOn603
        cmpli   0,0,r3,CPU_TYPE_604E
        bc      12,2,dCacheOn604
        cmpli   0,0,r3,CPU_TYPE_604R
        bc      12,2,dCacheOn604
	bclr	0x14,0x0		/* invalid cpu type */

dCacheOn603:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCE */
	ori	r3,r3,0x4000

	mfspr	r4,HID0		/* Modify HID0 to enable D cache (DCE) */
	or	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */

dCacheOn604:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCE */
	ori	r3,r3,0x4000

	mfspr	r4,HID0		/* Modify HID0 to enable D cache (DCE) */
	or	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */


/******************************************************************************
*
* dCacheOff - Turn Data Cache Off
*
* void dCacheOff (void)
*/

_dCacheOff:
dCacheOff:
	/* Get cpu type */

	mfspr	r3,PVR
	rlwinm	r3,r3,16,16,31

	cmpli	0,0,r3,CPU_TYPE_603
	bc	12,2,dCacheOff603
	cmpli	0,0,r3,CPU_TYPE_604
	bc	12,2,dCacheOff604
	cmpli	0,0,r3,CPU_TYPE_603E
	bc	12,2,dCacheOff603
        cmpli   0,0,r3,CPU_TYPE_603P
        bc      12,2,dCacheOff603
        cmpli   0,0,r3,CPU_TYPE_750
        bc	12,2,dCacheOff603
        cmpli   0,0,r3,CPU_TYPE_604E
        bc      12,2,dCacheOff604
        cmpli   0,0,r3,CPU_TYPE_604R
        bc      12,2,dCacheOff604
	bclr	0x14,0x0		/* invalid cpu type */

dCacheOff603:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCE */
	ori	r3,r3,0x4000	

	mfspr	r4,HID0		/* Modify HID0 to disable D cache (DCE) */
	andc	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */

dCacheOff604:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCE */
	ori	r3,r3,0x4000

	mfspr	r4,HID0		/* Modify HID0 to disable D cache (DCE) */
	andc	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */


/******************************************************************************
*
* dCacheInval - Invalidate Data Cache
*
* void dCacheInval (void)
*/

_dCacheInval:
dCacheInval:
	/* Get cpu type */

	mfspr	r3,PVR
	rlwinm	r3,r3,16,16,31

	cmpli	0,0,r3,CPU_TYPE_603
	bc	12,2,dCacheInval603
	cmpli	0,0,r3,CPU_TYPE_604
	bc	12,2,dCacheInval604
	cmpli	0,0,r3,CPU_TYPE_603E
	bc	12,2,dCacheInval603
        cmpli   0,0,r3,CPU_TYPE_603P
        bc      12,2,dCacheInval603
        cmpli   0,0,r3,CPU_TYPE_750
        bc	12,2,dCacheInval603
        cmpli   0,0,r3,CPU_TYPE_604E
        bc      12,2,dCacheInval604
        cmpli   0,0,r3,CPU_TYPE_604R
        bc      12,2,dCacheInval604
	bclr	0x14,0x0		/* invalid cpu type */

	/*
	 * To invalidate the Data Cache on a 603/750, it's necessary
	 * to toggle the DCFI bit.
	 */

dCacheInval603:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCFI */
	ori	r3,r3,0x0400

	mfspr	r4,HID0		/* Modify HID0 to SET DCFI bit */
	or	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */

	andc	r4,r4,r3	/* Modify HID0 to CLEAR DCFI bit */
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */

	/*
	 * To invalidate the Data Cache on a 604, it's necessary
	 * to toggle the DCFI bit while the Data Cache is enabled (DCE).
	 * It is also necessary to delay between setting and clearing DCFI.
	 */

dCacheInval604:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCFI + DCE */
	ori	r3,r3,0x4400

	mfspr	r4,HID0		/* Modify HID0 to SET DCFI + DCE bits */
	or	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */

	addis	r5,r0,0x0000		/* Setup for small delay */
	ori	r5,r5,0x1000
	mtspr	CTR,r5			/* Load PPC Counter reg */
dCacheInval604Loop:
	nop
	bdnz	dCacheInval604Loop	/* branch till counter reaches zero */

	andc	r4,r4,r3	/* Modify HID0 to CLEAR DCFI + DCE bits */
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */
#endif	/* INCLUDE_ECC */