target.nr

mtx603在vxworks下的bsp模板源代码

.ne 6
.sp .5
Raven MPIC IRQ	Priority	IRQ Source
_
IRQ0	8	Winbond PIB [all ISA interrupts]
IRQ1	0	Falcon ECC Error
IRQ2	14	Ethernet
IRQ3	3	SCSI
IRQ4	0	Graphics [not available]
IRQ5	N/A	[Not used]
IRQ6	N/A	[Not used]
IRQ7	N/A	[Not used]
IRQ8	N/A	[Not used]
IRQ9	0	PCI PMC1/PMC2 INTA
IRQ10	13	PCI PMC1/PMC2 INTB
IRQ11	2	PCI PMC1/PMC2 INTC
IRQ12	0	PCI PMC1/PMC2 INTD
IRQ13	0	[Not used]
IRQ14	N/A	[Not used]
IRQ15	N/A	[Not used]
.TE

For further details, refer to the appropriate board's reference guide.

There are only four PCI bus interrupts: A, B, C, and D.  They are shared among
all PCI bus devices and do not have levels.  PCI bus interrupts are wired
directly to the MPIC and, therefore, have pre-assigned system vector numbers
and interrupt levels.  The user enables one or more PCI interrupts and connects
vectored ISRs to the system by following these steps:

.IP "1)"
Identify the PCI interrupt letter(s) as required by
the application. Based on this, identify the
associated system interrupt level from the following
tables:

            Primary PCI Bus
            ----------------
            A = PMC_INT_LVL1
            B = PMC_INT_LVL2
            C = PMC_INT_LVL3
            D = PMC_INT_LVL4

            Secondary PCI Bus
            -----------------
            A = PMC_INT_LVL4
            B = PMC_INT_LVL3
            C = PMC_INT_LVL2
            D = PMC_INT_LVL1

.IP "2)"
Define the vector for each PCI interrupt as follows:
INT_VEC_IRQ0 + PMC_INT_LVLx where x is 1, 2, 3, or 4,
as determined above.
.IP "3)"
In the application code, perform intConnect() for
each vector and its associated ISR.
.IP "4)"
Perform sysIntEnable() for each identified system 
interrupt level.
.IP "5)"
When the application has finished, perform
sysIntDisable() for each identified level.

.SS "Serial Configuration"
The MTX600 board family has four serial ports.  All are ISA bus devices.
Two, serial port 1 (COM1 or console) and serial port 2 (COM2),
originate from the PC87308 Super I/O (SIO) chip.  The SIO serial ports are
functional equivalents to those in an Intel 8250 UART.

The other two serial ports, Serial Ports 3 and 4, are implemented in the
Zilog Z85230 ESCC chip and the Zilog Z8536 CIO chip (DTR and DSR lines).  They
can be configured as synchronous serial ports but no support for this mode is
provided by this BSP.

By default, all serial ports are configured as asynchronous, 9600 baud, with
1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software
handshake.  Hardware handshake using RTS/CTS is a supported option on all ports.

.SS "SCSI Configuration"
Only the SCSI-2 bus standard is supported.  The MTX600 board family
supports an 8-bit SCSI bus.

.SS "Network Configuration"
The MTX600 has both AUI and RJ45 (twisted pair) jack for Ethernet.  The RJ45
can be used with either 10baseT or 100baseTX.  The Ethernet driver
automatically senses and configures the port as 10baseT or 100baseTX.
The Ethernet driver is compatible with both DEC21040 and DEC21140 devices.

The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM contained in the DEC21140 chip.  If the address is not found in
serial ROM, the driver attempts to read it from NVRAM.

.SS "PCI Access"
The 32-bit PCI bus is fully supported under the \f2PCI Local Bus Specification,
Revision 2.1.\f1  The 64-bit extensions are not supported.  All configuration
space accesses are made with BDF (bus number, device number, function number)
format calls in the pciConfigLib module.  For more information, refer to the 
reference entries \f2mv260x_pciXxx\f1.

.SS "PCI Access in the Pseudo-PReP Memory Model" 1

The default pseudo-PReP mapping from the PCI bus point of view is:

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI I/O Space Access
.sp .5
Start	Size	Access to
_
0x00000000	8MB	PCI I/O space
0x00000000	64KB	ISA I/O space
.TE

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI MEM Space Access
.sp .5
Start	Size	Access to
_
0x80000000	16MB (min)	DRAM space
0x7C000000	256KB (fixed)	MPIC REGS
.TE

.SS "Boot Devices"
The supported boot devices are:

    \f3dc\f1 - Ethernet (10baseT or 100baseTX or AUI)

Motorola's Open Firmware and PPC1-Bug can be used to download and run VxWorks.
Consult the relevant user's manuals for details.

.SS "Boot Methods"
The boot methods are affected by the boot parameters.  If no password is
specified, RSH (remote shell) protocol is used.  If a password is specified,
FTP protocol is used, or, if the flag is set, TFTP protocol is used.

.SS "ROM Considerations"
Use the following command sequence on the host to re-make the BSP boot ROM:
.CS    
    cd target/config/mv260x
    make clean
    make bootrom.bin
    cp bootrom.bin /tftpboot/boot.bin
.CE

Power down the board and switch the ROM jumper to select socketed FLASH.
Connect the Ethernet and console serial port cables, then power the board back
up.

.SS "Flashing the Boot ROM Using Motorola PPC1-Bug:" 1

At the PPC1-Bug prompt, set up the network transfer from a TFTP host using 
`niot'.  Important: You must have a TFTP server running on your host's
subnet for the `niop' command to succeed.  Using `niot', the Client IP Address,
Server IP Address, and Gateway IP Address must be set up for the user's
specific environment:

.CS
   PPC1-Bug>niot
   Controller LUN =00?
   Device LUN     =00?
   Node Control Memory Address =00FA0000?
   Client IP Address      =123.123.10.100? 123.321.12.123
   Server IP Address      =123.123.18.105? 123.321.21.100
   Subnet IP Address Mask =255.255.255.0?
   Broadcast IP Address   =255.255.255.255?
   Gateway IP Address     =123.123.10.254? 123.321.12.254
   Boot File Name ("NULL" for None)     =? .

   Update Non-Volatile RAM (Y/N)? y
   PPC1-Bug>
.CE

The file is transferred from the TFTP host to the target board using
the `niop' command.  The file name must be set to the location
of the binary file on the TFTP host.  The binary file must be stored
in the directory identified for TFTP accesses, but the file name is
a relative path and does not include the \f3/tftpboot\f1 directory name:

.CS
   PPC1-Bug>niop
   Controller LUN =00?
   Device LUN     =00?
   Get/Put        =G?
   File Name      =? boot.bin
   Memory Address =00004000? 
   Length         =00000000?
   Byte Offset    =00000000?

   PPC1-Bug>
.CE

After the file is loaded onto the target, the `pflash' command is used
to put it into soldered FLASH parts.

.CS
   PPC1-Bug>pflash 4000:100000 ff000100
.CE

When the command is finished, power down the board and switch the ROM
jumper to select soldered FLASH.  Then power the board back up.

.SS "Flashing the Boot ROM Using Motorola Open Firmware:" 1

From the "ok" prompt on the console, use the `load' command to get the image
into RAM.  You must have a TFTP server running on your host's subnet for the
`load' command to succeed.  The command takes the following form:

.CS
    load /pci/ethernet@e:<host IP>,<file path/name>,<target IP>[,<gateway IP>]
.CE

.SS Note: 1
The modifiable parameter \f3load-base\f1 is set to the load-address of a
binary image to be loaded.  The factory preset value is 0x400000.

For example, \f3load-base\f1 must be modified to allow for the reserved 0x100
bytes at the beginning of a VxWorks boot image:

.CS
  ok load-base h# 100 + to load-base

  ok load /pci/ethernet@e:144.191.1.8,boot.bin,144.191.1.7

  Boot device: /pci/ethernet@e:144.191.1.8,boot.bin,144.191.1.7
  File and args:

  ok load-base h# 100 - to load-base
.CE

From the "ok" prompt, determine the starting memory address of soldered FLASH:

.CS
  ok 50 fal-l@
  fef80050  ff0b0006
            ^^^
.CE

Use the indicated first three nibbles followed by five zeros as the start
address.  In this example, the start address is ff000000.
(Note: "58 fal-l@" would return the socketed FLASH start address.)

From the "ok" prompt, use the \f3gflash\f1 command to program the image into
FLASH.  The command takes the following form:

.CS
    <start addr> <size> <flash start addr> (gflash)
.CE

To load the boot image into soldered FLASH, modify \f3load-base\f1 as follows:

.CS
  ok load-base 100000 ff000000 (gflash)

  Erasing ...
  Programming ...
  Verifying ....
  ok
.CE

Power down the board and switch the ROM jumper to select soldered FLASH.  Then
power the board back up.

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information concerning this BSP and its
use.

The config.h macro "INCLUDE_ECC" is disabled by default.
If the Motorola PPC1 Debugger/Diagnostics monitor ROM program
reports the following when starting: 

"System Memory: 32MB, ECC NOT Enabled (Non-ECC-Memory Detected)"

Then you may not enable INCLUDE_ECC in config.h for your board, else
it will fail to boot.

.SS "Delivered Objects"
The delivered objects are: `bootrom_uncmp', `vxWorks', `vxWorks.sym', and
`vxWorks.st'.

.SS "Make Targets"
The make targets are listed as the names of object-format files.  Append `.hex'
to each to derive a hex-format file name.

.nf
`bootrom'
`bootrom_uncmp'
`bootrom_res_high'  (bootrom_res does not build)
`vxWorks' (with vxWorks.sym)
`vxWorks_rom'
`vxWorks.st'
`vxWorks.st_rom'
`vxWorks.res_rom_res_low' (vxWorks.res_rom does not build)
`vxWorks.res_rom_nosym_res_low' (vxWorks.res_rom_nosym does not build)
.fi

.SS "Special Routines"
For these boards, the value of the CPU clock speed is read from the CPU 
configuration register using the macro MEMORY_BUS_SPEED which is defined
in mv2600.h.  For example:

.CS
   clkFreqMhz = MEMORY_BUS_SPEED;
.CE

.SS "Known Problems"
The Motorola Raven chip has a flaw which ignores PCI bus `LOCK' signals during
access of local memory from the PCI bus.  A new chip (Raven 3) is forthcoming
from Motorola and addresses this flaw.

Contact a Motorola representative for details on the new chips.

.SH "BOARD LAYOUT"
The diagram below shows flash EEPROM locations and jumpers relevant to VxWorks
configuration:

.ne 4i

.bS
___________________________________________________________________________
|                           MTX60x                                         |
| J37 (ROM ctrl) -> D                                                      |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|            ----                                                          |
|            ====                                                          |
|            ==== <== VxWorks Boot Flash                                   |
|            ====     (soldered)                                           |
|            ----                                                          |
|                                                                          |
|                                                                          |
|                    +----+   +----+                                       |
|   PPC1-Bug   ==> X |    | X |    |                                       |
|                  U |    | U |    |                                       |
|                  2 +----+ 1 +----+                                       |
|                                                                          |
|       COM 1                 10/100 BaseT                                 |
|______--------_________________--------___________________________________|
.bE
    Key: 
    X  vertical jumper installed
    :  vertical jumper absent
    -  horizontal jumper installed
    "  horizontal jumper absent
    0  switch off
    1  switch on
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed
    L  three-pin horizontal jumper, left jumper installed
    R  three-pin horizontal jumper, right jumper installed

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration"

.SH "BIBLIOGRAPHY"
.iB "Motorola MTX Series Single Board Computer Programmer's Reference Guide,"
.iB "Motorola PowerPC 603 RISC Microprocessor User's Manual,"
.iB "Motorola PowerPC 604 RISC Microprocessor User's Manual,"
.iB "Motorola PowerPC Microprocessor Family: The Programming Environments,"
.iB "Motorola MPC2604GA Integrated Secondary Cache for PowerPC Microprocessors (Glance) Data Sheets,"
.iB "Cirrus Logic Alpine VGA Family - CL-GD543X/4X Technical Reference Manual,"
.iB "DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual,"
.iB "National Semiconductor PC87308VUL (Super I/O Enhanced Sidewinder Lite) PC Controller Manual,"
.iB "SGS-Thompson MK48T59/559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet,"
.iB "SYM53Cxx (was NCR53C8xx) Family PCI-SCSI I/O Processors Programming Guide,"
.iB "Zilog SCC (Serial Communications Controller) User's Manual,"
.iB "Zilog ZCIO Counter/Timer and Parallel I/O Unit User's Manual,"
.iB "Winbond W83C553 Enhanced System I/O Controller with PCI Arbiter Data Book,"
.iB "IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC),"
.iB "IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC),"
.iB "IEEE Standard 1284 Bidirectional Parallel Port Interface Specification,"
.iB "Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1,"
.iB "PCI to PCI Bridge Architecture Specification 2.0,"
.iB "ANSI X3.131.1990 Small Computer System Interface-2 (SCSI-2) Draft Document"