target.nr

mtx603在vxworks下的bsp模板源代码

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.\" PowerPlus/target.nr - Motorola PowerPlus target-specific documentation
.\"
.\" Copyright 1984-2002 Wind River Systems, Inc.
.\" Copyright 1996,1999 Motorola, Inc., All Rights Reserved
.\"
.\" modification history
.\" --------------------
.\" 01u,29apr02,sbs  updated documentation and corrected PCI memory map
.\"                  (SPR 28535)  
.\" 01t,27aug01,dgp  change manual pages to reference entries per SPR 23698
.\" 01s,17jul99,dmw  added MTXPlus support.
.\" 01r,10mar99,jkf  added comment about ECC. SPR#25649.
.\" 01q,29oct98,mas  updated with latest changes from mv2603/target.nr, 01v.
.\" 01p,19may98,db   replaced references to pciIomapLib with pciConfigLib. 
.\" 01o,10aug97,tb   added support for MTX
.\" 01n,10oct97,srr  change name from NexGen to PowerPlus.
.\" 01m,27aug97,dgp  doc: final editing
.\" 01l,13aug97,mas  split into seperate files for each board family.
.\" 01k,24jul97,mas  added VME interrupt info and guidelines; added MPIC
.\"		     priority scheme (SPR 8956).
.\" 01j,17jul97,mas  added dynamic memory sizing info (SPR 8824).
.\" 01i,09jul97,mas  added serial ports 3 & 4 (SPR 8566) and PPC1-Bug flash ROM 
.\"                  info.  Rewritten to meet new guidelines.
.\" 01h,30apr97,mas  added extended VME, mv360x and mv230x info (SPR 8410).
.\" 01g,02apr97,dat  added VME config info, SPR 8271, fixed model nbr table
.\" 01f,05mar97,mas  changed GET_CPU_SPEED to MEMORY_BUS_SPEED; deleted ref to
.\"		     CPU_SPEED_MHZ; added tftp server required to burn flash
.\"		     (SPR 8114).
.\" 01e,18feb97,mas  clarified use of transition modules and board diagram
.\"                  (SPR 7772, 7811, 7832).
.\" 01d,10jan97,dat  cleaned up flash loading documentation
.\"             mas
.\" 01c,02jan97,wlf  doc: cleanup.
.\" 01b,01jan97,dat  added mod history
.\" 01a,01sep96,mot  written (Motorola Comp. Grp)
.\"
.\"
.TH "mtx60x" T "Motorola PowerPlus" "Rev: 10 Oct 97" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola MTX603, MTX604"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks.  Before using a board with VxWorks, verify that the board runs in the
factory configuration by using vendor-supplied ROMs and jumper settings and
checking the RS-232 connection.

The Motorola PowerPlus series of boards consists of four families: MVME230x,
MVME260x, MVME360x, and MTX60x.  This BSP encompasses only the MTX60x family.

The MTX60x board family consists of single-board computers based on the
PowerPC 603 and 604 microprocessors.  The MTX600 family is a non-VMEbus
version of the MVME2600.  The series part numbers are of the form:

    MTX60p-0nfa

    where
        p   = processor type
            3 = MPC603e
            4 = MPC604ev
        n   = number of CPUs
            0 = 1 CPU
            1 = 2 CPUs
        f   = feature set
            too numerous to itemize
        a   = not an option

For example, an MTX604-001a denotes a PowerPC 604ev mother board running at
200 MHz with two PMC site.

.SS "Boot ROMS"
The MTX600 boards have two sets of flash EEPROM (FLASH).  One set of two
AMD Am29F040 FLASH is socketed (sockets XU1 and XU2) and contains Motorola's
Open Firmware or, on later revisions, Motorola's PPC1-Bug.  The other set of 
E28f400 FLASH is soldered in.  The VxWorks boot kernel resides in the soldered 
FLASH.  See \f2Hardware Details: ROM Considerations\f1 for information about 
loading and writing the boot kernel image to the soldered FLASH.

These boards have non-volatile RAM; thus, boot parameters are preserved
whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
\f2Tornado User's Guide: Getting Started.\f1

.SS "Jumpers"
The following jumpers are relevant to VxWorks configuration: 

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l lw(2.6i) .
.ne 6
MTX60x
.sp .5
Jumper	Function	Description
_
J37	ROM controller	T{
Install the jumper across pins 2 and 3 to select the socketed FLASH.
Install the jumper across pins 1 and 2 to select the soldered FLASH
(factory configuration).
T}
.TE

For details of jumper configuration, see the board diagram at the end of
this entry and in the hardware manual.

Note that ROM controller jumpers should be set to select socketed FLASH until
VxWorks boot code is written to soldered FLASH, after which the jumpers should
be restored to the factory configuration of soldered FLASH.

.SH "FEATURES"
The following subsections list all supported and unsupported features, as well
as any feature interaction.

.SS "Supported Features"
The following features of the MTX600 board family are supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
Processors	T{
MPC603, MPC604; 33 and 66MHz bus clock
T}
L2 Cache	T{
256KB look-aside cache, write-through only
T}
FLASH	T{
4 or 8MB soldered (64-bit wide; 8-bit access), 1MB socketed (16-bit wide).
Soldered used for VxWorks boot image.
T}
DRAM	T{
16, 32, 64, 128, 256MB, two-way interleaved; auto-sized or fixed
T}
NVRAM	T{
8KB (MK48T59/559)
8KB
T}
Peripherals	T{
serial ports COM1 and COM2;
two sync/async serial ports;
8-bit single-ended fast SCSI-2 interface;
EIDE interface;
I2C interface (Philips 8584 for MTX, Falcon two-wire for MTXPlus);
AUI and 10baseT/100baseTX Ethernet interface
T}
ISA Interface	T{
full 64KB memory and I/O space
T}
PCI Interface	T{
32-bit address, 32-bit data; complies with \f2PCI Local Bus Specification\f1,
Revision 2.1
T}
Miscellaneous	T{
RESET switch
T}
.TE

.SS "Unsupported Features"
The following board features are not supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
Processors	T{
Dual Capability
T}
DRAM	T{
ECC protection
T}
RTC	T{
MK48T59/559; only NVRAM portion is used
T}
Peripherals	T{
PS/2 keyboard port;
PS/2 mouse port;
PS/2 floppy disk port;
IEEE1284/printer parallel port
T}
ISA Interface	T{
ISA RTC and DMA controllers
T}
PCI Interface	T{
64-bit data
T}
Miscellaneous	T{
ABORT switch, 6 status LEDs
T}
.TE

.SS "Feature Interactions"
None known.

.SH "HARDWARE DETAILS"
This section details device drivers and board hardware elements.

.SS "Devices"
The device drivers and libraries included with this BSP:

.nf
    `i8250Sio' - Intel 8250 UART driver (serial ports 1 and 2)
    `ppcDecTimer' - PowerPC decrementer timer driver (system and timestamp clock)
    `if_dc' - 10baseT/100baseTX DEC 21140 Ethernet driver (primary LAN)
    `byteNvRam' - byte-oriented generic non-volatile RAM driver
    `sl82565IntrCtl' - PIB interrupt controller driver
    `ravenMpic' - Motorola Raven MPIC interrupt controller driver
    `pciConfigLib' - PCI configuration library
    `z8530Sio' - Zilog Z8530 SCC/Z85230 ESCC driver (serial ports 3 and 4)
    `ppcZ8536Timer' - Zilog Z8536 timer driver (auxiliary clock)
    `ncr810Lib' - NCR 53C875 SCSI controller library
    `ataDrv' - EIDE controller driver
.fi

The `sl82565IntrCtl' module implements the Winbond W83C353 PCI-to-ISA Bridge
(PIB) driver.  The module was developed originally for the Symphonic
Laboratories SL82565 PIB which has been succeeded by the Winbond device.

.SS "Memory Maps"
On-board RAM for these boards always appears at address 0x0 locally.

Dynamic memory sizing is supported.  By default, LOCAL_MEM_AUTOSIZE is
defined so memory is auto-sized at hardware initialization time.
The default fixed RAM size is set to 16MB (see LOCAL_MEM_SIZE in config.h).

.SS "Pseudo-PReP Memory Model"
The following table describes the modified PowerPC Reference Platform (PReP)
address map created from the CPU point of view.  Tornado-compatible mapping
deviates only slightly from the model.

.TS E
expand;
lf3 lf3 lf3
l l lw(1.8i) .
.ne 6
.sp .5
Start	Size	Access to
_
0x0	LOCAL_MEM_SIZE (16MB min)	DRAM
LOCAL_MEM_SIZE	(0x80000000 - LOCAL_MEM_SIZE)	[Not used]
0x80000000	64KB	PCI ISA I/O space
0x81000000	8MB	PCI I/O space	
0xC0000000	64KB	PCI ISA MEM space
0xC1000000	16MB	PCI MEM space
0xD8000000	128MB	T{
PCI MEM (max. A32 VME space)
T}
0xE0000000	16MB	T{
PCI MEM (A24 VME space)
T}
0xE1000000	0x0EFF0000	[Not used]
0xEFFF0000	64KB	T{
PCI MEM (A16 VME space)
T}
0xF0000000	64KB	T{
PCI MEM (VME REG. (A32) space)
T}
0xF0010000	0x0BFF0000	[Not used]
0xFC000000	256KB	MPIC Reg space
0xFC040000	0x02F40000	[Not used]
0xFEF80000	128KB	Falcon/Raven regs.
0xFEFA0000	0x00060000	[Not used]
0xFF000000	16MB	T{
ROM space (No PCI)
T}
.TE

.SS "Extended PCI Memory Model"
The following table describes the alternative extended PCI memory 
address map created from the CPU's point of view.  This address mapping
is activated by defining EXTENDED_PCI.  The intent is to provide a 
3GB PCI memory mapping to support the MTXPlus PCI-PCI bridge and user installed
PCI cards.

.TS E
expand;
lf3 lf3 lf3
l l lw(1.8i) .
.ne 6
.sp .5
Start	Size	Access to
_
0x0	LOCAL_MEM_SIZE (16MB min)	DRAM
LOCAL_MEM_SIZE	(0x40000000 - LOCAL_MEM_SIZE)	[Not used]
0x40000000	0xBC000000	PCI MEM space (3GB)
0xFC000000	256KB	MPIC Reg space
0xFC040000	0x02F40000	[Not used]
0xFD000000	0x1F80000	PCI I/O space (32MB)
0xFEF80000	128KB	Falcon/Raven regs.
0xFEFA0000	0x00060000	[Not used]
0xFF000000	16MB	T{
ROM space (No PCI)
T}
.TE

.SS "Shared Memory"
The MTX600 does not support Shared Memory because it does not support the
VMEbus.

.SS "Interrupts"
The system interrupt vector table has 256 entries.  Vectors for the various
devices on the buses are assigned hierarchically as follows:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
00 - 0f	ISA IRQ numbers 0 - 15
10 - 1f	All MPIC interrupts
20 - 23	Raven timers
24 - 27	Raven interprocessor dispatch
   28  	Raven detected internal errors
29 - ff	[User defined]
.TE

The specific ISA vector number assignments are:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
   02	[Cascade interrupt from PIC2]
   03	COM2
   04	COM1
   09	Aux timers; serial ports 3 and 4
.TE

Vector numbers not in the table are not used by this BSP.

The standard ISA Intel 8259 Programmable Interrupt Controllers (PICs) assert
their interrupts through the Raven MPIC as an external interrupt.  The external
interrupt vector numbers are:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
   10	ISA PICs
   11	Falcon-ECC error
   12	PCI Ethernet
   13	PCI SCSI
   19	PCI PMC1/PMC2 INTA
   1a	PCI PMC1/PMC2 INTB
   1b	PCI PMC1/PMC2 INTC
   1c	PCI PMC1/PMC2 INTD
.TE

Vector numbers not in the table are not used by this BSP.

The Raven Multi-Processor Interrupt Controller (MPIC) sets system interrupt
priorities and serves as controller of all external interrupts.  Each
of its 16 interrupt control registers, designated IRQ0 through IRQ15, can be
programmed with a relative priority from 15, the highest, to 0, the lowest.  A
priority of zero effectively disables the interrupt.  All but one of the 16
control registers has been hardwired to a particular interrupt source.  The IRQ
number and priority assignments are as follows:

Note that the z8536 is emulated by a PAL on the MTXPlus.  Board fail and Abort
interrupts are supported while the CIO interrupt is not.  If INCLUDE_MPIC is
not defined, there is not Aux Clock support on MTXPlus.

.TS E
expand;
lf3 lf3 lf3
l l lw(2.6i) .