mtx.h

mtx603在vxworks下的bsp模板源代码

/* CHRP PCI mapping */

/* disable address space 0 for PCI MEM space */

#define CPU2PCI_ADDR0_START_VAL 0x0000
#define CPU2PCI_ADDR0_END_VAL   0x0000
#define CPU2PCI_OFFSET0_VAL     ((0x0-CPU2PCI_ADDR0_START_VAL) & 0xffff)
#define CPU2PCI_MSATT0_VAL      CPU2PCI_MSATT_DISABLED

/* setup address space 1 for PCI MEM, for MPIC regs */

#define CPU2PCI_ADDR1_START_VAL	(MPIC_BASE_ADRS >> 16)
#define CPU2PCI_ADDR1_END_VAL	(((MPIC_BASE_ADRS + 0x00ffffff) \
                                  >> 16) & 0x0000ffff)
#define CPU2PCI_OFFSET1_VAL	0x0
#define CPU2PCI_MSATT1_VAL	CPU2PCI_MSATT_MEM

/* setup address space 2 for PCI MEM */

#define CPU2PCI_ADDR2_START_VAL	(PCI_MSTR_MEMIO_LOCAL >> 16)
#define CPU2PCI_ADDR2_END_VAL	(((PCI_MSTR_MEMIO_LOCAL + \
								 (PCI_MSTR_MEM_SIZE-1)) >> 16) & 0x0000ffff)
#define CPU2PCI_OFFSET2_VAL		((0x0-CPU2PCI_ADDR2_START_VAL) & 0xffff)

/* setup address space 3 for PCI I/O */

#define CPU2PCI_ADDR3_START_VAL	(ISA_MSTR_IO_LOCAL    >> 16)
#define CPU2PCI_ADDR3_END_VAL	(((ISA_MSTR_IO_LOCAL + 0x17fffff) \
                                  >> 16) & 0x0000ffff)
#define CPU2PCI_OFFSET3_VAL	((0x0-CPU2PCI_ADDR3_START_VAL) & 0xffff)

#endif /* EXTENDED_PCI */

/* defines that are used in ravenPci.c */

#define CPU2PCI_ADDR0_START	CPU2PCI_ADDR0_START_VAL
#define CPU2PCI_ADDR0_END	CPU2PCI_ADDR0_END_VAL
#define CPU2PCI_OFFSET0		CPU2PCI_OFFSET0_VAL
#define CPU2PCI_MSATT0		CPU2PCI_MSATT0_VAL
#define CPU2PCI_ADDR1_START	CPU2PCI_ADDR1_START_VAL
#define CPU2PCI_ADDR1_END	CPU2PCI_ADDR1_END_VAL
#define CPU2PCI_OFFSET1		CPU2PCI_OFFSET1_VAL
#define CPU2PCI_MSATT1		CPU2PCI_MSATT1_VAL
#define CPU2PCI_ADDR2_START	CPU2PCI_ADDR2_START_VAL
#define CPU2PCI_ADDR2_END	CPU2PCI_ADDR2_END_VAL
#define CPU2PCI_OFFSET2		CPU2PCI_OFFSET2_VAL
#define CPU2PCI_MSATT2		CPU2PCI_MSATT_MEM
#define CPU2PCI_ADDR3_START	CPU2PCI_ADDR3_START_VAL
#define CPU2PCI_ADDR3_END	CPU2PCI_ADDR3_END_VAL
#define CPU2PCI_OFFSET3		CPU2PCI_OFFSET3_VAL
#define CPU2PCI_MSATT3		CPU2PCI_MSATT_IO

/* PCI to CPU definitions */

#ifdef LOCAL_MEM_AUTOSIZE
# define DRAM_SIZE		((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)
#else
# define DRAM_SIZE		(LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)
#endif

#define PCI2CPU_ADDR0_START     (PCI2DRAM_BASE_ADRS & 0xffff0000)
#define PCI2CPU_ADDR0_END	((PCI2DRAM_BASE_ADRS + DRAM_SIZE \
                                  - 0x10001) >> 16)
#define PCI2CPU_ADDR0_RANGE     (PCI2CPU_ADDR0_START | PCI2CPU_ADDR0_END)
#define PCI2CPU_OFFSET0         (((0x0-PCI2DRAM_BASE_ADRS)>>16) & 0x0000ffff)
#define PCI2CPU_ATT0            0xf2

#define PCI2CPU_ADDR1_START     ((PCI2DRAM_BASE_ADRS + DRAM_SIZE \
                                  - 0x10000) & 0xffff0000)
#define PCI2CPU_ADDR1_END       ((PCI2DRAM_BASE_ADRS + DRAM_SIZE \
                                  - 0x10000) >> 16)
#define PCI2CPU_ADDR1_RANGE     (PCI2CPU_ADDR1_START | PCI2CPU_ADDR1_END)
#define PCI2CPU_OFFSET1         (((0x0-PCI2DRAM_BASE_ADRS)>>16) & 0x0000ffff)
#define PCI2CPU_ATT1            0xe2

/*
 * Address decoders 2 and 3 are not currently used, so they are
 * set to point to an address that is not used on the PCI bus
 */
#define PCI2CPU_ADDR2_RANGE     0xfff0fff0
#define PCI2CPU_OFFSET2         0x0
#define PCI2CPU_ATT2            0x0
#define PCI2CPU_ADDR3_RANGE     0xfff0fff0
#define PCI2CPU_OFFSET3         0x0
#define PCI2CPU_ATT3            0x0

#ifndef INCLUDE_MPIC

/* PCI IACK for ISA */

#define ISA_INTR_ACK_REG	(CPU_PCI_IACK_ADRS + 0x1ff0)

#endif /* !INCLUDE_MPIC */

/* pc87303 ISA super IO device (ISASIO) keybrd, serial, Parallel port */

#define pc87303_KBD_CTRL	(ISA_MSTR_IO_LOCAL + 0x0064)	/* keyboard */
#define pc87303_INDX_REG	(ISA_MSTR_IO_LOCAL + 0x0398)	/* index reg */
#define pc87303_DATA_REG	(ISA_MSTR_IO_LOCAL + 0x0399)	/* data reg */
#define pc87303_PP		(ISA_MSTR_IO_LOCAL + 0x03bc)	/* parallel */
#define pc87303_COM1		(ISA_MSTR_IO_LOCAL + 0x03f8)	/* serial 1 */
#define pc87303_COM2		(ISA_MSTR_IO_LOCAL + 0x02f8)	/* serial 2 */
#define pc87303_FDC		(ISA_MSTR_IO_LOCAL + 0x03f0)	/* floppy */

/* z85230 synchronous & Asynchronous serial communications chip */

#define z85230_PORTB_CTRL	(ISA_MSTR_IO_LOCAL + 0x0840)	/* serial 4 */
#define z85230_PORTB_DATA	(ISA_MSTR_IO_LOCAL + 0x0841)	
#define z85230_PORTA_CTRL	(ISA_MSTR_IO_LOCAL + 0x0842)	/* serial 3 */
#define z85230_PORTA_DATA	(ISA_MSTR_IO_LOCAL + 0x0843)

/* z8536 aux timer and I/O chip */

#define	z8536_PORTC_DATA	(ISA_MSTR_IO_LOCAL + 0x0844)
#define	z8536_PORTB_DATA	(ISA_MSTR_IO_LOCAL + 0x0845)
#define	z8536_PORTA_DATA	(ISA_MSTR_IO_LOCAL + 0x0846)
#define	z8536_PORT_CTRL		(ISA_MSTR_IO_LOCAL + 0x0847)
#define ZCIO_CNTRL_ADRS		(UINT8 *)(ISA_MSTR_IO_LOCAL + 0x847)
#define ZCIO_IACK_ADRS		(UINT8 *)(ISA_MSTR_IO_LOCAL + 0x84F)

/* m48TXX non volatile ram, RTC and watchdog timer */

#define m48TXX_LSB_REG		(ISA_MSTR_IO_LOCAL + 0x0074)
#define	m48TXX_MSB_REG		(ISA_MSTR_IO_LOCAL + 0x0075)
#define m48TXX_DAT_REG		(ISA_MSTR_IO_LOCAL + 0x0077)

#ifdef        INCLUDE_I2C
 
/* I2C registers */
 
#define I2C_CTRL_REG		(ISA_MSTR_IO_LOCAL + 0x0981)
#define I2C_CMD_STAT		(ISA_MSTR_IO_LOCAL + 0x0980)
 
#endif /* INCLUDE_I2C */

/* CPU type */

#define CPU_TYPE		((vxPvrGet() >> 16) & 0xffff)
#define CPU_TYPE_601		0x01	/* PPC 601 CPU */
#define CPU_TYPE_602		0x02	/* PPC 602 CPU */
#define CPU_TYPE_603		0x03	/* PPC 603 CPU */
#define CPU_TYPE_603E		0x06    /* PPC 603e CPU */
#define CPU_TYPE_603P		0x07    /* PPC 603p CPU */
#define CPU_TYPE_750		0x08    /* PPC 750 CPU */
#define CPU_TYPE_604		0x04	/* PPC 604 CPU */
#define CPU_TYPE_604E		0x09	/* PPC 604e CPU */
#define CPU_TYPE_604R		0x0A	/* PPC 604r CPU */

/* L2CR register (MPC750 - Arthur) */

#define MPC750_L2CR_E		0x80000000
#define MPC750_L2CR_256K	0x10000000
#define MPC750_L2CR_512K	0x20000000
#define MPC750_L2CR_1024K	0x30000000
#define MPC750_L2CR_I		0x00200000
#define MPC750_L2CR_SL		0x00008000
#define MPC750_L2CR_IP		0x00000001

/* System Configuration register */

#define SYS_REG_GCR		((unsigned int *)(FALCON_BASE_ADRS + 0x08))
#define SYS_REG_GCR_MSK 	0x0000011e
#define SYS_REG_GCR_FREF	0x00000008
#define SYS_REG_GCR_DRAM_70ns	0x00000000
#define SYS_REG_GCR_DRAM_60ns	0x00000002
#define SYS_REG_GCR_DRAM_50ns	0x00000006

#define SYS_REG_CCR_ 		(FALCON_BASE_ADRS + 0x400)
#define SYS_REG_CCR		((unsigned int *)(FALCON_BASE_ADRS + 0x400))

#define SYS_REG_CCR_ID_MSK	0xff000000	/* System ID mask */
#define SYS_REG_CCR_MTX		0xfb000000	/* MTX board type */
#define SYS_REG_CCR_GEN2x	0xfe000000	/* genesis 2.x board type */
#define SYS_REG0_CCR_2300	0xfd000000      /* hummingbird board type */

#define SYS_REG_CCR_CLK_MSK	0x00f00000	/* Bus clock Mask */
#define SYS_REG_CCR_CPU_CLK_66	0x00f00000 /* cpu external Bus clock 66 Mhz */
#define SYS_REG_CCR_CPU_CLK_60	0x00e00000 /* cpu external Bus clock 60 Mhz */
#define SYS_REG_CCR_CPU_CLK_50	0x00d00000 /* cpu external Bus clock 50 Mhz */

#define SYS_REG_CCR_SYSXC_MSK	0x000f0000	/* lookaside l2 cache mask */
#define SYS_REG_CCR_SYSXC_256	0x000e0000	/* lookaside 256kb L2 cache */
#define SYS_REG_CCR_SYSXC_512	0x000d0000	/* lookaside 512kb L2 cache */
#define SYS_REG_CCR_SYSXC_1024	0x000c0000	/* lookaside 1Mb L2 cache */
#define SYS_REG_CCR_SYSXC_NC	0x000f0000	/* lookaside no cache */

#define SYS_REG_CCR_P0STAT_MSK	0x0000f000	/* in-line l2 cache mask */
#define SYS_REG_CCR_P0STAT_256	0x00006000	/* in-line 256kb L2 cache */
#define SYS_REG_CCR_P0STAT_512	0x00005000	/* in-line 512kb L2 cache */
#define SYS_REG_CCR_P0STAT_1024	0x00004000	/* in-line 1Mb L2 cache */
#define SYS_REG_CCR_P0STAT_NC	0x00007000	/* in-line no cache */

/* DRAM configuration registers */

#define SYS_REG_MCR_ 		(FALCON_BASE_ADRS + 0x404)
#define SYS_REG_MCR		((unsigned int *)(FALCON_BASE_ADRS + 0x404))

#define SYS_REG_MCR_FREF_UNK 	0x10000000
#define SYS_REG_MCR_FREF_TRUE	0x10000000
#define SYS_REG_MCR_FREF_FALSE	0x00000000

#define SYS_REG_MCR_DRAM_MSK 	0x03000000
#define SYS_REG_MCR_DRAM_50ns	0x03000000
#define SYS_REG_MCR_DRAM_60ns	0x01000000
#define SYS_REG_MCR_DRAM_70ns	0x00000000

#define SYS_REG_MCR_ROMAB_MSK	0x00700000
#define SYS_REG_MCR_ROMAB_ITL	0x00600000
#define SYS_REG_MCR_ROMAB_UNK	0x00700000

#define SYS_REG_MCR_L2TYPE_MSK	0x0000F000
#define SYS_REG_MCR_L2TYPE_LWP	0x00000000
#define SYS_REG_MCR_L2TYPE_BP	0x00001000
#define SYS_REG_MCR_L2TYPE_LWNP	0x00002000
#define SYS_REG_MCR_L2TYPE_BNP	0x00003000

#define SYS_REG_MCR_L2PLL_MSK	0x00000F00
#define SYS_REG_MCR_L2PLL_DIS	0x00000000
#define SYS_REG_MCR_L2PLL_1_1	0x00000100
#define SYS_REG_MCR_L2PLL_3_2	0x00000200
#define SYS_REG_MCR_L2PLL_2_1	0x00000300
#define SYS_REG_MCR_L2PLL_5_2	0x00000400
#define SYS_REG_MCR_L2PLL_3_1	0x00000500

#define SYS_REG_MCR_FLASH_MSK	0x00000038
#define SYS_REG_MCR_FLASH_1M 	0x00000000
#define SYS_REG_MCR_FLASH_2M 	0x00000008
#define SYS_REG_MCR_FLASH_4M 	0x00000010
#define SYS_REG_MCR_FLASH_8M 	0x00000018
#define SYS_REG_MCR_FLASH_16M	0x00000020
#define SYS_REG_MCR_FLASH_32M	0x00000028
#define SYS_REG_MCR_FLASH_64M	0x00000030
#define SYS_REG_MCR_FLASH_NO 	0x00000038

#define DRAM_REG_SIZE           (FALCON_BASE_ADRS + 0x10)
#define DRAM_REG_BASE           (FALCON_BASE_ADRS + 0x18)

/* Base Module Feature Register */

#define SYS_REG_CCR_OLD		((char *)(ISA_MSTR_IO_LOCAL + 0x0800))
#define SYS_REG_BMFR		((char *)(ISA_MSTR_IO_LOCAL + 0x0802))

#define SYS_REG_BMFR_EIDE	0x80	/* EIDE ports present */
#define SYS_REG_BMFR_SCCP	0x40	/* z85230 sync serial Port */
#define SYS_REG_BMFR_PCI2P	0x20	/* pmc or 32-bit PCI present */
#define SYS_REG_BMFR_PCI1P	0x10	/* pmc or 32-bit PCI present */
#define SYS_REG_BMFR_PCI3P	0x08	/* 64-bit PCI present */
#define SYS_REG_BMFR_GFXP	0x04	/* graphics Present */
#define SYS_REG_BMFR_LANP	0x02	/* ethernet Present */
#define SYS_REG_BMFR_SCIP	0x01	/* scsi present */

#define DEVICE_PRESENT(x) 	(!((*SYS_REG_BMFR) & (x)))

/* Base Module Status Register */

#define SYS_REG_BMSR		((char *)(ISA_MSTR_IO_LOCAL + 0x0803))

#define SYS_REG_BMSR_MCP750	0xe0	/* Standard Mesquite */
#define SYS_REG_BMSR_MCP750_CIG	0xe1	/* Mesquite configured for CIG */
#define SYS_REG_BMSR_MTX_PLUS	0xf6	/* MTX Plus */
#define SYS_REG_BMSR_MTX	0xf7	/* MTX without Parallel Port */
#define SYS_REG_BMSR_MTX_PP	0xf8	/* MTX with Parallel Port */
#define SYS_REG_BMSR_2300	0xf9    /* Hummingbird */
#define SYS_REG_BMSR_2300_E	0xfa    /* Hummingbird - E */
#define SYS_REG_BMSR_100BT4	0xfa	/* SlimGen with 712 and 100B T4 */
#define SYS_REG_BMSR_SG712	0xfb	/* Slim Gen with 712 */
#define SYS_REG_BMSR_SG761	0xfc	/* Slim Gen with 761 */
#define SYS_REG_BMSR_FG712	0xfd	/* Full Gen with 712 */
#define SYS_REG_BMSR_FG761	0xfe	/* Full Gen with 761 */
#define SYS_REG_BMSR_1600	0xff	/* MV1600 */

/* Assembly define for L2 cache */

#define SYS_REG_SXCCR_A		(FALCON_BASE_ADRS + 0x8000)

/* defines for L2 cache routines */

#define SYS_REG_SXCCR		((unsigned char *)(FALCON_BASE_ADRS + 0x8000))

#define L2_DISABLE		0x80
#define L2_RESET		0x40
#define L2_ENABLE		0x80
#define L2_FLUSH		0x10
#define L2_END_FLUSH		0x10
#define L2_FLUSH_LOOP		4100

/* z8536 I/O port bit mapping */

#define z8536_PORTA_BRDFAIL	0x40
#define z8536_PORTB_FUSE	0x40
#define z8536_PORTB_ABORT	0x80

/*
 * Raven Extensions to Standard PCI Header
 *
 * Type declarations for the PCI Header and the macros in regards to the
 * PCI BUS.  These definitions have been made with respect to PCI LOCAL
 * BUS SPECIFICATION REVISION 2.1.  Every device on the PCI BUS has to
 * support 256 bytes of configuration space of which the first 64 bytes
 * are a predefined header portion defined by the PCI commitee.  Bytes
 * 64 to 255 are dedicated to the device specific registers.
 *
 * Note: the PCI bus is inherently little endian. 
 */

#define PCI_CFG_RAVEN_PSADD0	0x80
#define PCI_CFG_RAVEN_PSATT0	0x84
#define PCI_CFG_RAVEN_PSOFF0	0x86
#define PCI_CFG_RAVEN_PSADD1	0x88
#define PCI_CFG_RAVEN_PSATT1	0x8c
#define PCI_CFG_RAVEN_PSOFF1	0x8e
#define PCI_CFG_RAVEN_PSADD2	0x90
#define PCI_CFG_RAVEN_PSATT2	0x94
#define PCI_CFG_RAVEN_PSOFF2	0x96
#define PCI_CFG_RAVEN_PSADD3	0x98
#define PCI_CFG_RAVEN_PSATT3	0x9c
#define PCI_CFG_RAVEN_PSOFF3	0x9e

/* Raven MPC registers */

#define RAVEN_MPC_VENID		0x00
#define RAVEN_MPC_DEVID		0x02
#define RAVEN_MPC_REVID		0x05
#define RAVEN_MPC_GCSR		0x08
#define RAVEN_MPC_FEAT		0x0a
#define RAVEN_MPC_MARB		0x0e
#define RAVEN_MPC_PADJ		0x13
#define RAVEN_MPC_MEREN		0x22
#define RAVEN_MPC_MERST		0x27
#define RAVEN_MPC_MERAD		0x28
#define RAVEN_MPC_MERAT		0x2e
#define RAVEN_MPC_PIACK		0x30
#define RAVEN_MPC_MSADD0	0x40
#define RAVEN_MPC_MSOFF0	0x44
#define RAVEN_MPC_MSATT0	0x47
#define RAVEN_MPC_MSADD1	0x48
#define RAVEN_MPC_MSOFF1	0x4c
#define RAVEN_MPC_MSATT1	0x4f
#define RAVEN_MPC_MSADD2	0x50
#define RAVEN_MPC_MSOFF2	0x54
#define RAVEN_MPC_MSATT2	0x57
#define RAVEN_MPC_MSADD3	0x58
#define RAVEN_MPC_MSOFF3	0x5c
#define RAVEN_MPC_MSATT3	0x5f
#define RAVEN_MPC_WDT1CNTL	0x60
#define RAVEN_MPC_WDT2CNTL	0x68
#define RAVEN_MPC_GPREG0_U	0x70
#define RAVEN_MPC_GPREG0_L	0x74
#define RAVEN_MPC_GPREG1_U	0x78
#define RAVEN_MPC_GPREG1_L	0x7c

/*
 * Raven register bit masks
 *
 * Bits marked with 'C' indicate conditions which can be cleared by
 * writing a 1 to the bits.
 */

/* Raven MPC Error Enable (MEREN) register bit masks */

#define RAVEN_MPC_MEREN_RTAI	0x0001	/* PCI mstr Recvd Target Abort Int */
#define RAVEN_MPC_MEREN_SMAI	0x0002	/* PCI mstr Signld Target Abort Int */
#define RAVEN_MPC_MEREN_SERRI	0x0004	/* PCI System Error Int */
#define RAVEN_MPC_MEREN_PERRI	0x0008	/* PCI Parity Error Int */
#define RAVEN_MPC_MEREN_MATOI	0x0020	/* MPC Address Bus Time-out Int */
#define RAVEN_MPC_MEREN_RTAM	0x0100	/* RTAI machine check enable */
#define RAVEN_MPC_MEREN_SMAM	0x0200	/* SMAI machine check enable */
#define RAVEN_MPC_MEREN_SERRM	0x0400	/* SERRI machine check enable */
#define RAVEN_MPC_MEREN_PERRM	0x0800	/* PERRI machine check enable */