mtx.h

mtx603在vxworks下的bsp模板源代码

/* mtx.h - Motorola MTX PowerPlus board header */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998, 1999 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01d,10jul02,pmr  SPR 79573: defines for SCSI component.
01c,09jul02,jrp  Fixed PCI write posting problem on boot (SPR #78589).
01b,16sep01,dat  Use of WRS_ASM macro
01a,02jun99,dmw  Created based on mv2600.h, 01h,19jan99.
*/

/*
This file contains I/O addresses and related constants for the
Motorola PowerPlus MTX board family. 
*/

#ifndef	INCmtxh
#define	INCmtxh

#ifdef __cplusplus
extern "C" {
#endif

/* ATA/EIDE support */

#include "drv/pcmcia/pccardLib.h"
#include "drv/hdisk/ataDrv.h"

/* Floppy disk support */

#define FD_MAX_DRIVES 	4
#define FD_BASE_ADDR	pc87303_FDC	/* See super I/O section */
#define FD_DMA_CHAN	2

#ifdef	INCLUDE_FD
#   ifndef	INCLUDE_DOSFS
#       define	INCLUDE_DOSFS	/* file system to be used */
#   endif
#   ifndef	INCLUDE_ISADMA
#       define	INCLUDE_ISADMA	/* uses ISA DMA driver */
#   endif
#endif

/* Boot Line parameters are stored in the 2nd 256 byte block */

#undef	NV_BOOT_OFFSET
#define NV_BOOT_OFFSET		256 /* skip 1st 256 bytes */
#define NV_RAM_SIZE    		BBRAM_SIZE		
#define NV_RAM_ADRS    		((char *) BBRAM_ADRS)
#define NV_RAM_INTRVL           1

/* PCI to PCI bridge setup values */

#define P2P_IO_SPACE_BASE_ADRS  ((P2P_IO_BASE & 0x0000F000) >> 8)
#define P2P_IO_SPACE_LIMIT_ADRS ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0x0000F000)
#define P2P_IO_HI16_BASE_ADRS   ((P2P_IO_BASE & 0xFFFF0000) >> 16)
#define P2P_IO_HI16_LIMIT_ADRS  ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0xFFFF0000)
#define P2P_NPMEM_SPACE_BASE_ADRS ((P2P_NONPREF_MEM_BASE & 0xFFFF0000) >> 16)
#define P2P_NPMEM_SPACE_LIMIT_ADRS ((P2P_NONPREF_MEM_BASE + \
                                     P2P_NONPREF_MEM_SIZE - 1) & 0xFFFF0000)
#define P2P_PREF_MEM_BASE_ADRS  ((P2P_PREF_MEM_BASE & 0xFFFF0000) >> 16)
#define P2P_PREF_MEM_LIMIT_ADRS ((P2P_PREF_MEM_BASE + P2P_PREF_MEM_SIZE - 1) & \
                                 0xFFFF0000)

/* PCI I/O function defines */

#define INT_NUM_IRQ0            INT_VEC_IRQ0

#ifndef _ASMLANGUAGE

extern	UINT sysGetBusSpd (void);

#ifndef PCI_IN_BYTE
#define PCI_IN_BYTE(x)          sysPciInByte (x)
IMPORT  UINT8                   sysPciInByte  (UINT32 address);
#endif
#ifndef PCI_IN_WORD
#define PCI_IN_WORD(x)          sysPciInWord (x)
IMPORT  UINT16                  sysPciInWord  (UINT32 address);
#endif
#ifndef PCI_IN_LONG
#define PCI_IN_LONG(x)          sysPciInLong (x)
IMPORT  UINT32                  sysPciInLong  (UINT32 address);
#endif
#ifndef PCI_OUT_BYTE
#define PCI_OUT_BYTE(x,y)       sysPciOutByteConfirm (x,y)
IMPORT  void                    sysPciOutByte (UINT32 address, UINT8  data);
IMPORT  void                    sysPciOutByteConfirm (UINT32 address, UINT8  data);
#endif
#ifndef PCI_OUT_WORD
#define PCI_OUT_WORD(x,y)       sysPciOutWordConfirm (x,y)
IMPORT  void                    sysPciOutWord (UINT32 address, UINT16 data);
IMPORT  void                    sysPciOutWordConfirm (UINT32 address, UINT16 data);
#endif
#ifndef PCI_OUT_LONG
#define PCI_OUT_LONG(x,y)       sysPciOutLongConfirm (x,y)
IMPORT  void                    sysPciOutLong (UINT32 address, UINT32 data);
IMPORT  void                    sysPciOutLongConfirm (UINT32 address, UINT32 data);
#endif

#endif  /* _ASMLANGUAGE */

/* Cache Line Size - 32 32-bit value = 128 bytes */

#define PCI_CLINE_SZ		0x20

/* Latency Timer value - 255 PCI clocks */

#define PCI_LAT_TIMER		0xff

/* clock rates */

/* Calculate Memory Bus Rate in Hertz */

#define MEMORY_BUS_SPEED                (sysGetBusSpd() * 1000000)

/* System clock (decrementer counter) frequency determination */

#define DEC_CLOCK_FREQ          ((sysGetBusSpd()==67)?66666666:33333333)

/* CIO clocks and stuff */

#define CIO_RESET_DELAY		5000
#define ZCIO_HZ			2500000 /* 2.5 MHz clock */
#define CIO_INT_VEC		9
#define Z8536_TC		ZCIO_HZ

/*
 * The PowerPC Decrementer is used as the system clock.
 * It is always included in this BSP.  The following defines
 * are used by the system clock library.
 */

#define SYS_CLK_RATE_MIN  	10		/* minimum system clock rate */
#define SYS_CLK_RATE_MAX  	5000		/* maximum system clock rate */

/*
 * This macro returns the positive difference between two unsigned ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)	( abs((int)a - (int)b) )

/*
 * Auxiliary Clock support is an optional feature that is not supported
 * by all BSPs.  The following defines are used by the aux clock library.
 */

#define AUX_CLK_RATE_MIN  	40		/* min auxiliary clock */
#define AUX_CLK_RATE_MAX	5000		/* max auxiliary clock rate */

/* Common I/O synchronizing instructions */

#ifndef EIEIO_SYNC
#define EIEIO_SYNC  WRS_ASM(" eieio; sync")
#endif  /* EIEIO_SYNC */
#ifndef EIEIO
#define EIEIO    WRS_ASM(" eieio")
#endif  /* EIEIO */

/* Translation macro */

#define TRANSLATE(x,y,z)\
        ((UINT)(x) - (UINT)(y) + (UINT)(z))

/* Legacy ISA space size. Reserved for kybd, com1, com2,... */

#define ISA_LEGACY_SIZE		0x00004000

#define ISA_MSTR_IO_SIZE	0x00010000	/* 64 kbytes (includes legacy) */

#define ISA_MSTR_IO_BUS		0x00000000	/* must be zero */
#define PCI_MSTR_MEMIO_BUS	0x00000000	/* 0 based addressing */

/* Extended PCI address map. */

#ifdef EXTENDED_PCI

/* ISA I/O space within PCI I/O space (includes ISA legacy space) */

#    define ISA_MSTR_IO_LOCAL	0xfd000000  /* base of ISA I/O space */

/* Access to PCI nonprefetchable memory space (including ISA memory space) */

#    define PCI_MSTR_MEMIO_LOCAL	0x40000000

#else /* PReP map */

/* ISA I/O space within PCI I/O space (includes ISA legacy space) */

#    define ISA_MSTR_IO_LOCAL	0x80000000

/* Access to PCI nonprefetchable memory space (including ISA memory space) */

#    define PCI_MSTR_MEMIO_LOCAL	0xc0000000   /* base of ISA mem space */

#endif /* EXTENDED_PCI */

/* For backward compatibility */

#define CPU_PCI_ISA_IO_ADRS	ISA_MSTR_IO_LOCAL

/* PCI I/O space (above ISA I/O space) */

/*
 * NOTE: (PCI_MSTR_IO_LOCAL+PCI_MSTR_IO_SIZE) must be less than
 *        PCI_MSTR_MEMIO_LOCAL to prevent overlap.
 */

#define PCI_MSTR_IO_LOCAL	(ISA_MSTR_IO_LOCAL+ISA_MSTR_IO_SIZE)
#define PCI_MSTR_IO_BUS		(TRANSLATE(PCI_MSTR_IO_LOCAL,\
				 ISA_MSTR_IO_LOCAL,\
				 ISA_MSTR_IO_BUS))

/* PCI (pre-fetchable) Memory space (above ISA memory space) */

#define PCI_MSTR_MEM_LOCAL	(PCI_MSTR_MEMIO_LOCAL+PCI_MSTR_MEMIO_SIZE)
#define PCI_MSTR_MEM_BUS	(TRANSLATE(PCI_MSTR_MEM_LOCAL,\
				 PCI_MSTR_MEMIO_LOCAL,\
				 PCI_MSTR_MEMIO_BUS))

#ifndef INCLUDE_MPIC
/*
 * All starting addresses are correct except for CPU_PCI_IACK_ADRS.
 * This address was selected to allow a minimum 8k memory range
 * for the MMU table entry.
 */

#define CPU_PCI_IACK_ADRS	0xbfffe000	/* covers PCI IACK space */
						/* base = 0xbffffff0; */
#define CPU_PCI_IACK_SIZE	0x00002000	/* 8 kbytes */

#define MPIC_ADDR(reg)		(MPIC_BASE_ADRS + reg)
#define MPIC_GLOBAL_CONFIG_REG	0x01020
#define RESET_CNTRLR		0x80000000

#endif  /* !INCLUDE_MPIC */

/* Base address of HW devices as seen from CPU */

#define FALCON_BASE_ADRS	0xfef80000
#define FALCON_REG_SIZE		0x00010000
#define FALCON_BASE_UPPER_ADRS	(FALCON_BASE_ADRS>>16)
#define FALCON_DRAM_ATTR	0xfef80010
#define FALCON_RESET_STAT_U	0xfef80400
#define RAVEN_BASE_ADRS		0xfeff0000
#define RAVEN_REG_SIZE		0x00010000
#define FLASH_BASE_ADRS		0xFF000000
#define FLASH_MEM_SIZE		0x01000000

/* MPIC configuration defines */

#define MPIC_BASE_ADRS		0xfc000000
#define MPIC_REG_SIZE		0x00040000
#ifndef EXTENDED_PCI
#define MPIC_PCI_BASE_ADRS	( MPIC_BASE_ADRS - PCI_MSTR_MEMIO_LOCAL )
#else
#define MPIC_PCI_BASE_ADRS	MPIC_BASE_ADRS
#endif /* EXTENDED_PCI */

/* memory map as seen on the PCI bus */

#define PCI_CNFG_ADRS		0x00800000      /* base of PCI config space */

#define PCI2DRAM_BASE_ADRS	0x80000000      /* memory seen from PCI bus */

/*
 * Primary PCI bus configuration space address and data register addresses
 * as seen by the CPU on the local bus.
 */

#define PCI_PRIMARY_CAR		(ISA_MSTR_IO_LOCAL + 0xCF8) /* cfg addr reg */
#define PCI_PRIMARY_CDR		(ISA_MSTR_IO_LOCAL + 0xCFC) /* cfg data reg */

/* PCI Device/Vendor IDs */

#define PCI_ID_RAVEN		0x48011057      /* Id for RAVEN ASIC */
#define PCI_ID_IBC		0x056510ad      /* Id for W83C553 PIB */
#define PCI_ID_LN_DEC21040	0x00021011      /* Id DEC chip 21040 */
#define PCI_ID_LN_DEC21140	0x00091011      /* Id DEC chip 21140 */
#define PCI_ID_LN_DEC21143	0x00191011      /* Id DEC chip 21143 */
#define PCI_ID_BR_DEC21150	0x00221011      /* Id DEC 21150 PCI bridge */
#define PCI_ID_NCR810		0x00011000      /* Id for SYM53C810A Chip */
#define PCI_ID_NCR860		0x00061000      /* Id for SYM53C860 Chip */
#define PCI_ID_NCR875		0x000f1000      /* Id for SYM53C875 Chip */
#define PCI_ID_SCSI		PCI_ID_NCR875	/* Id for Primary SCSI */
#define PCI_ID_SEC_SCSI		PCI_ID_NCR825	/* Id for Secondary SCSI */
#define PCI_ID_IDE		0x010510ad      /* Id for W83C553 IDE */
#define PCI_ID_NCR825		0x00031000      /* Id for SYM53C825/75 Chips*/
#define PCI_ID_5434		0x00a81013      /* Id for CL-GD534 chip */
#define PCI_ID_5436		0x00ac1013      /* Id for CL-GD536 chip */
#define PCI_ID_USB		0x30381106      /* USB (function 2 of PBC) */
#define PCI_ID_PM		0x30401106      /* Power Mgmt (func 3 of PBC */

/* Base address register defines */

#define PCI_BASEADDR_IO		(1<<0)  /* PCI I/O space */
#define PCI_BASEADDR_MEM	(0<<0)  /* PCI Memory space */
#define PCI_BASEADDR_MEM_TYPE	(3<<1)  /* memory type mask */
#define PCI_BASEADDR_MEM_32BIT	(0<<1)  /* map anywhere in 32-bit addr space */
#define PCI_BASEADDR_MEM_ONEMEG	(1<<1)  /* map below 1MB */
#define PCI_BASEADDR_MEM_64BIT	(2<<1)  /* map anywhere in 64-bit addr space */
#define PCI_BASEADDR_MEM_PREFETCH	(1<<3)  /* prefetchable */

/* cmd_reg defines */

#define PCI_CMDREG_IOSP		(1<<0)  /* Enable IO space accesses */
#define PCI_CMDREG_MEMSP	(1<<1)  /* Enable MEM space accesses */
#define PCI_CMDREG_MASTR	(1<<2)  /* Enable PCI Mastership */
#define PCI_CMDREG_SPCYC	(1<<3)  /* Monitor special cycles */
#define PCI_CMDREG_MEMWINV	(1<<4)  /* Enable memory write and invalidate */
#define PCI_CMDREG_VGASNP	(1<<5)  /* Enable VGA palette snooping */
#define PCI_CMDREG_PERR		(1<<6)  /* Enable Parity error response */
#define PCI_CMDREG_STEP		(1<<7)  /* Enable address/data stepping */
#define PCI_CMDREG_SERR		(1<<8)  /* Enable SERR driver */
#define PCI_CMDREG_FSTB2B	(1<<9)  /* Enable back to back transactions */

/* PCI Space Definitions  -- For configuring the RAVEN */

/* PPC Slave Attribute bit definitions */

#define CPU2PCI_ATTR_REN	(1<<7)  /* Read enable */
#define CPU2PCI_ATTR_WEN	(1<<6)  /* Write enable */
#define CPU2PCI_ATTR_WPEN	(1<<4)  /* Write post enable */
#define CPU2PCI_ATTR_MEM	(1<<1)  /* PCI memory cycle */
#define CPU2PCI_ATTR_IOM	(1<<0)  /* PCI I/O mode */

/* CPU to PCI definitions */

#define CPU2PCI_MSATT_MEM	( CPU2PCI_ATTR_REN | CPU2PCI_ATTR_WEN | \
				  CPU2PCI_ATTR_MEM )

#define CPU2PCI_MSATT_IO	( CPU2PCI_ATTR_REN | CPU2PCI_ATTR_WEN )
#define CPU2PCI_MSATT_DISABLED  ( CPU2PCI_MSATT_MEM & ~( CPU2PCI_ATTR_REN | \
						         CPU2PCI_ATTR_WEN ) )


#ifndef EXTENDED_PCI
/* STANDARD ( PReP ) mapping of PCI space */

/* disable PCI address space 0 */

#define CPU2PCI_ADDR0_START_VAL 0x0000
#define CPU2PCI_ADDR0_END_VAL   0x0000
#define CPU2PCI_OFFSET0_VAL     ((0x0-CPU2PCI_ADDR0_START_VAL) & 0xffff)
#define CPU2PCI_MSATT0_VAL      CPU2PCI_MSATT_DISABLED

/* disable PCI address space 1 */

#define CPU2PCI_ADDR1_START_VAL 0x0000
#define CPU2PCI_ADDR1_END_VAL   0x0000
#define CPU2PCI_OFFSET1_VAL     ((0x0-CPU2PCI_ADDR1_START_VAL) & 0xffff)
#define CPU2PCI_MSATT1_VAL      CPU2PCI_MSATT_DISABLED

/* setup address space 2 for PCI MEM space */

#define CPU2PCI_ADDR2_START_VAL	(PCI_MSTR_MEMIO_LOCAL >> 16)
#define CPU2PCI_ADDR2_END_VAL	((MPIC_BASE_ADRS + 0x00ff0000) >> 16)
#define CPU2PCI_OFFSET2_VAL		((0x0-CPU2PCI_ADDR2_START_VAL) & 0xffff)

/* setup address space 3 for PCI I/O space */

#define CPU2PCI_ADDR3_START_VAL	(ISA_MSTR_IO_LOCAL    >> 16)
#define CPU2PCI_ADDR3_END_VAL	((PCI_MSTR_MEMIO_LOCAL - 1) >> 16)
#define CPU2PCI_OFFSET3_VAL		((0x0-CPU2PCI_ADDR3_START_VAL) & 0xffff)

#else