syslib.c

wind river提供的MPC8260的BSP典型代码

/* sysLib.c - system-dependent library */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01f,29mar02,kab  SPR 74100: remove #include sysTffs.c for T2.2
01e,12dec01,pch  Add nullVme driver
01d,24sep01,g_h  move SIO, TIMER, EEPROM driver to be localy
01c,07may01,g_h  add support for visionWARE 2.00
01d,21oct99,elk  fixed system hang sysToMonitor() when using ^X to reboot 
01c,19aug99,elk  added local bus SDRAM and 4Mb/2Mb flash in sysPhysMemDesc.
01b,19apr99,elk  added support for Ethernet.
01a,05mar99,elk	 adopted from estMDP8xx/sysLib.c 
*/

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "stdio.h"
#include "taskLib.h" 
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/mmu603Lib.h"
#include "private/vmLibP.h"
#include "drv/mem/m8260Siu.h"
#include "drv/intrCtl/m8260IntrCtl.h"
#include "drv/parallel/m8260IOPort.h"
#include "smc8260Sio.h"
#if (NV_RAM_SIZE != NONE)
#include "eeprom.h"
#endif /* NV_RAM_SIZE != NONE */
#include "wrSbc8260.h"

/* Global data */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with caching and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {

    /* use IBAT0 to map flash execution space */
    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT ),

    /* The other IBATS are being disabled here.... */

    0, 0, /* I BAT 1 */

    0, 0, /* I BAT 2 */

    0, 0, /* I BAT 3 */

    /* use DBAT0 to map flash into data space */
    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT),

    /* use DBAT1 to map CPM DPRAM and internal registers into data space */
    /* NOTE! the internal space cannot be cached and should be guarded */
    ((INTERNAL_MEM_MAP_ADDR & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((INTERNAL_MEM_MAP_ADDR & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* use DBAT2 to map local bus SDRAM into data space -- if user wants it */
    /* NOTE! the local bus SDRAM cannot be cached -- period */
  #ifdef INCLUDE_LOCAL_BUS_SDRAM
    ((LOCAL_BUS_SDRAM_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_4M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((LOCAL_BUS_SDRAM_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT),
  #else
	0, 0, /* D BAT 2 */
  #endif /* INCLUDE_LOCAL_BUS_SDRAM */

    /* The other DBAT3 is being disabled here.... */

    0, 0, /* D BAT 3 */
    };

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64KB.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 *	Total mapped memory		Page Table size
 *	-------------------		---------------
 *	       8 Meg			     64 K
 *	      16 Meg			    128 K
 *	      32 Meg			    256 K
 *	      64 Meg			    512 K
 *	     128 Meg			      1 Meg
 *		.				.
 *		.				.
 *		.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
{
  /* The following maps the Vector Table and Interrupt Stack */
  {
    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_MEM_COHERENCY
  },

  /* The following maps the Local SDRAM */
  {
    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_MEM_COHERENCY
  },

  /* The following maps the 4Kb Board Control and Status */
  {
    (void *) BSCR_BASE_ADRS,
    (void *) BSCR_BASE_ADRS,
    0x00001000,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
  },

  /* The following maps the NV RAM memory */
  {
    (void *) NV_RAM_ADRS,
    (void *) NV_RAM_ADRS,
    NV_RAM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
  },

  /* The following maps the FLASH on CS0 to its actual physical address and size */
  {
    (void *) CS0_FLASH_ADRS,
    (void *) CS0_FLASH_ADRS,
    CS0_FLASH_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
  },

  /* The following maps the flash on CS6 to its actual physical address and size */
  {
    (void *) CS6_FLASH_ADRS,
    (void *) CS6_FLASH_ADRS,
    CS6_FLASH_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
  }
};

int sysPhysMemDescNumEnt = NELEMENTS( sysPhysMemDesc ) ;

int   sysBus       = BUS            ; /* system bus type (NONE)            */
int   sysCpu       = CPU            ; /* system CPU type (PPC8260)         */
char *sysBootLine  = BOOT_LINE_ADRS ; /* address of boot line              */
char *sysExcMsg    = EXC_MSG_ADRS   ; /* catastrophic message area         */
BOOL  sysVmeEnable = FALSE          ; /* by default no VME                 */
                                      /*                                   */
int   sysProcNum                    ; /* processor number of this CPU      */
int   sysFlags                      ; /* boot flags                        */
char  sysBootHost[ BOOT_FIELD_LEN ] ; /* name of host from which we booted */
char  sysBootFile[ BOOT_FIELD_LEN ] ; /* name of file from which we booted */

IMPORT unsigned char glbEnetAddr [];

/* 8260 Reset Configuration Table (From page 9-2 in Rev0 of 8260 book) */
#define END_OF_TABLE 0

struct config_parms {                
    UINT32 inputFreq;     /*          MODCK_H                        */
    UINT8  modck_h;       /*             |                           */
    UINT8  modck13;       /*             |MODCK[1-3]                 */
    UINT32 cpmFreq;       /*   Input     |  |     CPM          Core  */
    UINT32 coreFreq;      /*     |       |  |      |            |    */
    } modckH_modck13[] = {/*     V       V  V      V            V    */
                            {FREQ_33MHZ, 1, 0, FREQ_66MHZ,  FREQ_133MHZ},
                            {FREQ_33MHZ, 1, 1, FREQ_66MHZ,  FREQ_166MHZ},
                            {FREQ_33MHZ, 1, 2, FREQ_66MHZ,  FREQ_200MHZ},
                            {FREQ_33MHZ, 1, 3, FREQ_66MHZ,  FREQ_233MHZ},
                            {FREQ_33MHZ, 1, 4, FREQ_66MHZ,  FREQ_266MHZ},
                            {FREQ_33MHZ, 1, 5, FREQ_100MHZ, FREQ_133MHZ},
                            {FREQ_33MHZ, 1, 6, FREQ_100MHZ, FREQ_166MHZ},
                            {FREQ_33MHZ, 1, 7, FREQ_100MHZ, FREQ_200MHZ},
                            {FREQ_33MHZ, 2, 0, FREQ_100MHZ, FREQ_233MHZ},
                            {FREQ_33MHZ, 2, 1, FREQ_100MHZ, FREQ_266MHZ},
                            {FREQ_33MHZ, 2, 2, FREQ_133MHZ, FREQ_133MHZ},
                            {FREQ_33MHZ, 2, 3, FREQ_133MHZ, FREQ_166MHZ},
                            {FREQ_33MHZ, 2, 4, FREQ_133MHZ, FREQ_200MHZ},
                            {FREQ_33MHZ, 2, 5, FREQ_133MHZ, FREQ_233MHZ},
                            {FREQ_33MHZ, 2, 6, FREQ_133MHZ, FREQ_266MHZ},
                            {FREQ_33MHZ, 2, 7, FREQ_166MHZ, FREQ_133MHZ},
                            {FREQ_33MHZ, 3, 0, FREQ_166MHZ, FREQ_166MHZ},
                            {FREQ_33MHZ, 3, 1, FREQ_166MHZ, FREQ_200MHZ},
                            {FREQ_33MHZ, 3, 2, FREQ_166MHZ, FREQ_233MHZ},
                            {FREQ_33MHZ, 3, 3, FREQ_166MHZ, FREQ_266MHZ},
                            {FREQ_33MHZ, 3, 4, FREQ_200MHZ, FREQ_133MHZ},
                            {FREQ_33MHZ, 3, 5, FREQ_200MHZ, FREQ_166MHZ},
                            {FREQ_33MHZ, 3, 6, FREQ_200MHZ, FREQ_200MHZ},
                            {FREQ_33MHZ, 3, 7, FREQ_200MHZ, FREQ_233MHZ},
                            {FREQ_33MHZ, 4, 0, FREQ_200MHZ, FREQ_266MHZ},
			    {FREQ_66MHZ, 5, 5, FREQ_133MHZ, FREQ_133MHZ},
                            {FREQ_66MHZ, 5, 6, FREQ_133MHZ, FREQ_166MHZ},
                            {FREQ_66MHZ, 5, 7, FREQ_133MHZ, FREQ_200MHZ},
                            {FREQ_66MHZ, 6, 0, FREQ_133MHZ, FREQ_233MHZ},
                            {FREQ_66MHZ, 6, 1, FREQ_133MHZ, FREQ_266MHZ},
                            {FREQ_66MHZ, 6, 2, FREQ_133MHZ, FREQ_300MHZ},
                            {FREQ_66MHZ, 6, 3, FREQ_166MHZ, FREQ_133MHZ},
                            {FREQ_66MHZ, 6, 4, FREQ_166MHZ, FREQ_166MHZ},
                            {FREQ_66MHZ, 6, 5, FREQ_166MHZ, FREQ_200MHZ},
                            {FREQ_66MHZ, 6, 6, FREQ_166MHZ, FREQ_233MHZ},
                            {FREQ_66MHZ, 6, 7, FREQ_166MHZ, FREQ_266MHZ},
                            {FREQ_66MHZ, 7, 0, FREQ_166MHZ, FREQ_300MHZ},
                            {FREQ_66MHZ, 7, 1, FREQ_200MHZ, FREQ_133MHZ},
                            {FREQ_66MHZ, 7, 2, FREQ_200MHZ, FREQ_166MHZ},
                            {FREQ_66MHZ, 7, 3, FREQ_200MHZ, FREQ_200MHZ},
                            {FREQ_66MHZ, 7, 4, FREQ_200MHZ, FREQ_233MHZ},
                            {FREQ_66MHZ, 7, 5, FREQ_200MHZ, FREQ_266MHZ},
                            {FREQ_66MHZ, 7, 6, FREQ_200MHZ, FREQ_300MHZ},
                            {FREQ_66MHZ, 7, 7, FREQ_233MHZ, FREQ_133MHZ},
                            {FREQ_66MHZ, 8, 0, FREQ_233MHZ, FREQ_166MHZ},
                            {FREQ_66MHZ, 8, 1, FREQ_233MHZ, FREQ_200MHZ},
                            {FREQ_66MHZ, 8, 2, FREQ_233MHZ, FREQ_233MHZ},
                            {FREQ_66MHZ, 8, 3, FREQ_233MHZ, FREQ_266MHZ},
                            {FREQ_66MHZ, 8, 4, FREQ_233MHZ, FREQ_300MHZ},
                            {END_OF_TABLE,0,0,0,0}
                         };

/* Forward function references   */
UINT32  vxImmrGet (void);
void 	vxImmrSet (UINT32 value);
void	sysClkRateAdjust ( int * );
UINT32  sysChipRev(void);
void    sysCpmReset(void);
UINT8   sysUserSwitchGet(void);
UINT32  sysCoreFreqGet(void);
UINT32  sysCpmFreqGet(void);
UINT32  sysInputFreqGet(void);
UINT8   sysModck13Get (void);
UINT8   sysModckHGet (void);

/* locals */
LOCAL UINT32 immrAddress = (UINT32) INTERNAL_MEM_MAP_ADDR;

/* Additional Components */
#if (NV_RAM_SIZE == NONE)
#include "mem/nullNvRam.c"
#else
#include "eeprom.c"
#include "mem/byteNvRam.c"
#endif

#include "vme/nullVme.c"
#include "mem/m82xxDpramLib.c"
#include "sysSerial.c"
#include "intrCtl/m8260IntrCtl.c"
#include "timer/m8260Timer.c"

#ifdef INCLUDE_SYSLED
#include "sysLed.c"
#endif /* INCLUDE_SYSLED */

#include "sysIOPort.c"

#ifdef INCLUDE_CACHE_SUPPORT
#include "sysCacheLockLib.c"
#endif /* INCLUDE_CACHE_SUPPORT */

#ifdef INCLUDE_VWARE_LAUNCH
#include "sysVware.c"
#endif /* INCLUDE_VWARE_LAUNCH */

#ifdef  INCLUDE_NETWORK
#include "sysNet.h"
#include "sysNet.c"
#ifdef  INCLUDE_MOTFCCEND
#include "sysMotFccEnd.c"
#endif /* INCLUDE_MOTFCCEND */
#ifdef  INCLUDE_MOTSCCEND
#include "sysMotSccEnd.c"
#endif /* INCLUDE_MOTSCCEND */
#endif /* INCLUDE_NETWORK */

/***********************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/

char * sysModel
    ( 
    void 
    )
    {
    return( "MPC8260 PowerQUICC II -- Wind River. SBC8260" ) ;
    }

/***********************************************************************
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.2/0. BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev
    ( 
    void 
    )
    {
    return( BSP_VERSION BSP_REV );
    }

/***********************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various feature of the EST MPC8260 board. It sets
* up the control registers, initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/

void sysHwInit
    ( 
    void 
    )
    {
   volatile UINT32 temp;
   int             ix;
   ULONG         * pDPRAM1;

#ifdef INCLUDE_VWARE_LAUNCH
   char vwareMacAdrs[VWARE_MAC_ADRS_LEN];
#endif /* INCLUDE_VWARE_LAUNCH */

    /* Get the physical location of the IMMR register */
    int immrVal = vxImmrGet () ;

    /* Issue a Software Reset Command to the CPM core */
    sysCpmReset ();

    /* Initialize the LEDs */
    sysLedInit ();

    /* Initialize DPRAM1 to zero.  */
    pDPRAM1 = (unsigned long *)immrVal;

    for (ix = 0; ix < 0x1000; ix++)
        *pDPRAM1++ = 0;

    /*  reset port A, B, C, and D */
    *M8260_IOP_PAPAR( immrVal ) = 0x00000000;
    *M8260_IOP_PADIR( immrVal ) = 0x00000000;
    *M8260_IOP_PAODR( immrVal ) = 0x00000000;

    *M8260_IOP_PBPAR( immrVal ) = 0x00000000;
    *M8260_IOP_PBDIR( immrVal ) = 0x00000000;
    *M8260_IOP_PBODR( immrVal ) = 0x00000000;

    *M8260_IOP_PCPAR( immrVal ) = 0x00000000;
    *M8260_IOP_PCDIR( immrVal ) = 0x00000000;
    *M8260_IOP_PCSO ( immrVal ) = 0x00000000;

    *M8260_IOP_PDPAR( immrVal ) = 0x00000000;
    *M8260_IOP_PDDIR( immrVal ) = 0x00000000;
    *M8260_IOP_PDSO ( immrVal ) = 0x00000000;

    /*
     * Initialize SICR.
     */
    *M8260_SICR( immrVal ) = 0x00000000;

    /*
     * Initialize interrupts - default interrupt level.
     */
    m8260IntrInit ();

     
    if (sysChipRev() == SILICON_REV_PREA1)
        {
         temp = *M8260_SIUMCR( immrVal );
         temp &= 0xf3ffffff;    /* First clear DPPC ...   */
         temp |= 0x08000000;    /* ... then enable TBEN. */
         *M8260_SIUMCR( immrVal ) = temp;
        }

    /* 
     * Init the DPRAM lib 
     */

    m82xxDpramLibInit ();

    /*
     * Reset serial channels.
     */
    sysSerialHwInit ();
    
    /*
     * Setup port D for SMC1.
     */
    *M8260_IOP_PDPAR( immrVal ) |= (PD8 | PD9);
    *M8260_IOP_PDDIR( immrVal ) |=  PD9;

    /*
     * Setup port A for SMC2.
     */
    *M8260_IOP_PAPAR( immrVal ) |= (PA8 | PA9);
    *M8260_IOP_PADIR( immrVal ) |=  PA9;

#ifdef  FORCE_DEFAULT_BOOT_LINE
    strncpy(sysBootLine,DEFAULT_BOOT_LINE,strlen(DEFAULT_BOOT_LINE)+1);
#elif defined INCLUDE_VWARE_LAUNCH
    if (sysVwareBuildBootLine((char*)&vwareMacAdrs))
	{
	sysEnetAddrSet (vwareMacAdrs[0], 
			vwareMacAdrs[1], 
			vwareMacAdrs[2], 
			vwareMacAdrs[3],
			vwareMacAdrs[4],
			vwareMacAdrs[5]
		       );
	}
#endif /* FORCE_DEFAULT_BOOT_LINE */

    /* make sure Ethernet is disabled */

#ifdef INCLUDE_MOTSCCEND
    sysSccEnetDisable (0);
    sysSccEnetIntDisable (0);
#endif /* INCLUDE_MOTSCCEND */

#ifdef INCLUDE_MOTFCCEND
    sysFccEnetDisable (immrVal, 2);
#endif /* INCLUDE_MOTFCCEND */
    }

/***********************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* Normally, the user specifies the amount of physical memory with the
* macro LOCAL_MEM_SIZE in config.h.  BSPs that support run-time
* memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined.
* If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the
* true size of physical memory.
*
* NOTE: Do no adjust LOCAL_MEM_SIZE to reserve memory for application
* use.  See sysMemTop() for more information on reserving memory.
*
* RETURNS: The address of the top of physical memory.
*
* SEE ALSO: sysMemTop()
*/