sysmotfccend.c

wind river提供的MPC8260的BSP典型代码

			MOT_FCC_TBD_NUM,  	
			MOT_FCC_RBD_NUM,  	
			MOT_FCC_PHY_ADDR,  	
			MOT_FCC_DEF_PHY_MODE,  	
			&motFccAnOrderTbl,
			motFccFlags,
			MOT_FCC_MBLK_RBD_RATIO,
			MOT_FCC_CLUS_RBD_RATIO
		 );
        if ((pEnd = (END_OBJ *) motFccEndLoad  (paramStr)) == (END_OBJ *)NULL) 
            {
            logMsg ("Error: motFccEndLoad  failed to load driver\n", 0, 0, 0, 0, 0, 0);
            }
        }
    return pEnd;
    }

/***********************************************************************
*
* sysFccEnetEnable - enable the MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to enable the Ethernet device and to connect the MII interface to the FCC.
*
* RETURNS: OK, or ERROR if the FCC controller cannot be enabled.
*/
 
STATUS sysFccEnetEnable
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum		/* FCC being used */
    )
    {
    /* set Port B and C to use MII signals */

    *M8260_IOP_PCPAR(immrVal) |=  (PC19 | PC18);
    *M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
    *M8260_IOP_PCSO(immrVal)  &= ~(PC19 | PC18);
    *M8260_IOP_PCDIR(immrVal) &= ~(PC19 | PC18);

    *M8260_IOP_PBPAR(immrVal) |= (PB31 | PB30 | PB29 | PB28 | PB27 | PB26 | PB25 |
                                  PB24 | PB23 | PB22 | PB21 | PB20 | PB19 | PB18);
    *M8260_IOP_PBDIR(immrVal) |= (PB31 | PB29 | PB25 | PB24 | PB23 | PB22);
    *M8260_IOP_PBDIR(immrVal)&= ~(PB30 | PB28 | PB27 | PB26 | PB21 | PB20 | PB19 | PB18);
    *M8260_IOP_PBSO(immrVal) &= ~(PB31 | PB30 | PB28 | PB27 | PB26 | PB25 | PB24 | 
                                  PB23 | PB22 | PB21 | PB20 | PB19 | PB18);
    *M8260_IOP_PBSO(immrVal) |=  (PB29);

    /* connect FCC2 clocks */

    *M8260_CMXFCR (immrVal)  |= (0x00250000);
    *M8260_CMXFCR (immrVal)  &= ~(0x00400000);

    _func_motFccPhyDuplex = (FUNCPTR) 0;

    return (OK);
    }

/*********************************************************************** 
*
* sysFccEnetDisable - disable MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to disable the Ethernet device and the MII interface to the FCC
* controller.  This involves restoring the default values for all the Port
* B and C signals.
*
* RETURNS: OK, always.
*/
 
STATUS sysFccEnetDisable
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum		/* FCC being used */
    )
    {
    int intLevel = intLock ();
 
    /* 
     * configure all Port B and C pins previously used as general 
     * purpose input pins 
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC19 | PC18);

    *M8260_IOP_PCDIR(immrVal) &= ~(PC10);

    *M8260_IOP_PBPAR(immrVal) &= ~(PB31 | PB30 | PB29 | PB28 | PB27 | PB26 | PB25 |
                                   PB24 | PB23 | PB22 | PB21 | PB20 | PB19 | PB18);
    *M8260_IOP_PBDIR(immrVal) &= ~(PB31 | PB29 | PB25 | PB24 | PB23 | PB22);

    /* Disable the interrupt */

    intDisable (INUM_FCC2);

    intUnlock (intLevel);
 
    return (OK);
    }

/*********************************************************************** 
*
* sysFccEnetAddrGet - get the hardware Ethernet address
*
* This routine provides the six byte Ethernet hardware address that will be
* used by each individual FCC device unit.  This routine must copy
* the six byte address to the space provided by <addr>.
*
* RETURNS: OK, or ERROR if the Ethernet address cannot be returned.
*/

STATUS sysFccEnetAddrGet
    (
    int     unit,    /* not used - only slave SCC1 is wired to port */
    UINT8 * addr     /* Location address is returned in */
    )
    {
    STATUS status;

#if (BOOT_DEVICE == SCC_FCC_END)
    int index;
#endif /* (BOOT_DEVICE == SCC_FCC_END) */     

    /* Get MAC address */
    status = sysEnetAddrGet (unit, addr);

#if (BOOT_DEVICE == SCC_FCC_END)
    /* Add 1 to address, carry for last three bytes of MAC address */
    for (index = 5; index > 2; index--)
        {
        if (addr[index] == 0xff)
            {
            addr[index] = 0;
            /* 
             * next iteration will carry the 1, unless we are
             * out of room to modify the last 3 bytes       
             */
             }
        else
             {
            addr[index]++;
            /* no need to carry anymore */
            break;
            }
        }
#endif /* (BOOT_DEVICE == SCC_FCC_END) */ 

    return (status);
    }

/***********************************************************************
*
* sysFccEnetCommand - issue a command to the Ethernet interface controller
*
* this routine issue a command to the Ethernet interface controller
*
* RETURNS: OK, or ERROR if the Ethernet controller could not be restarted.
*/

STATUS sysFccEnetCommand
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    UINT16	command
    )
    {
    return (OK);
    }

#ifndef NSDELAY
#define MOTOROLA_FCC_LOOP_NS 2

#define NSDELAY(nsec)                                                   \
    {                                                                   \
    volatile int nx = 0;                                                \
    volatile int loop = (int)(nsec*MOTOROLA_FCC_LOOP_NS);               \
                                                                        \
    for (nx = 0; nx < loop; nx++);                                      \
    }
#endif /* NSDELAY */

/***********************************************************************
*
* sysFccMiiBitWr - write one bit to the MII interface
*
* This routine writes the value in <bitVal> to the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
* If <bitVal> is NONE, then the MDIO pin should be left in high-impedance
* state.
*
* SEE ALSO: sysFccMiiBitRd()
*
* RETURNS: OK, or ERROR.
*/
STATUS sysFccMiiBitWr
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    INT32        bitVal          /* the bit being written */
    )
    {
    miiBitWrCount++; 
    /* 
     * we create the timing reference for transfer of info on the MDIO line 
     * MDIO is mapped on PC9, MDC on PC10. We need to keep the same data
     * on MDIO for at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
    *M8260_IOP_PCDIR(immrVal) |=  (PC10 | PC9);
    *M8260_IOP_PCDAT(immrVal) |=  (PC10);

    switch (bitVal)
	{
	case 0:
	    *M8260_IOP_PCDAT(immrVal) &= ~(PC9);
	    break;
	case 1:
	    *M8260_IOP_PCDAT(immrVal) |= (PC9);
	    break;
	case ((INT32) NONE):
	    /* put it in high-impedance state */
	    *M8260_IOP_PCDIR(immrVal) &= ~(PC9);
	    break;
	default:
	    return (ERROR);
	}

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC10);

    NSDELAY (200);

    return (OK);
    }

/*********************************************************************** 
*
* sysFccMiiBitRd - read one bit from the MII interface
*
* This routine reads one bit from the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
*
* SEE ALSO: sysFccMiiBitWr()
*
* RETURNS: OK, or ERROR.
*/

STATUS sysFccMiiBitRd
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    INT8 *      bitVal          /* the bit being read */
    )
    {
    miiBitRdCount++; 
    /* 
     * we create the timing reference for transfer of info on the MDIO line 
     * MDIO is mapped on PC9, MDC on PC10. We can read data on MDIO after
     * at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
    *M8260_IOP_PCDIR(immrVal) &= ~(PC9);

    *M8260_IOP_PCDIR(immrVal) |= (PC10);
    *M8260_IOP_PCDAT(immrVal) |= (PC10);

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC10);

    NSDELAY (200);

    /* we can now read the MDIO data on PC9 */

    *bitVal = (*M8260_IOP_PCDAT(immrVal) & (PC9)) >> 22;
 
    return (OK);
    }

#endif /* INCLUDE_MOTFCCEND */