rominit.s

wind river提供的MPC8260的BSP典型代码

* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romMemcInit)

	mfspr	r30,LR

	/*
	 * CS0 16Meg, 8-bit Flash SIM
	 * CS6 2Meg, 8-bit Flash
	 */
#ifdef SIMM_FLASH_CS0
	lis	r5, HIADJ(0xfe001801)
	addi	r5, r5, LO(0xfe001801)
	stw	r5, INIT_BR0(r4)

	lis	r5, HIADJ(0xfe000856)
	addi	r5, r5, LO(0xfe000856)
	stw	r5, INIT_OR0(r4)
	
	lis	r5, HIADJ(0xe0000801)
	addi	r5, r5, LO(0xe0000801)
	stw	r5, INIT_BR6(r4)

	lis	r5, HIADJ(0xffe00060)
	addi	r5, r5, LO(0xffe00060)
	stw	r5, INIT_OR6(r4)
#endif

#ifdef LOCAL_FLASH_CS0
	lis	r5, HIADJ(0xfe000801)
	addi	r5, r5, LO(0xfe000801)
	stw	r5, INIT_BR0(r4)

	lis	r5, HIADJ(0xfe000856)
	addi	r5, r5, LO(0xfe000856)
	stw	r5, INIT_OR0(r4)
	
	lis	r5, HIADJ(0xe0001801)
	addi	r5, r5, LO(0xe0001801)
	stw	r5, INIT_BR6(r4)

	lis	r5, HIADJ(0xfe000856)
	addi	r5, r5, LO(0xfe000856)
	stw	r5, INIT_OR6(r4)
#endif

	bl	romMemcSdram60xBusInit

	bl	romMemcSdramLocalBusInit

	/*
	 * CS5: 32Kb, 8-bit, EEPROM.
	 */

	lis	r5, HIADJ(0xffff0860)
	addi	r5, r5, LO(0xffff0860)
	stw	r5, INIT_OR5(r4)
	
	lis	r5, HIADJ(0x22000801)
	addi	r5, r5, LO(0x22000801)
	stw	r5, INIT_BR5(r4)

	/*
	 * CS6: Set up in CS0 section
	 */

	/*
	 * CS7: User Switches/User LEDs
	 */

	lis	r5, HIADJ(0xffff03f6)
	addi	r5, r5, LO(0xffff03f6)
	stw	r5, INIT_OR7(r4)
	
	lis	r5, HIADJ(0x21000801)
	addi	r5, r5, LO(0x21000801)
	stw	r5, INIT_BR7(r4)

	/*
	 * CS8..CS11: Disabled
	 */

	lis	r5, HIADJ(0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, INIT_BR8(r4)
	stw	r5, INIT_BR9(r4)
	stw	r5, INIT_BR10(r4)
	stw	r5, INIT_BR11(r4)
	
	mtspr	LR,r30
	bclr	20,0
FUNC_END(romMemcInit)

/***************************************************************************
*
* romMemcSdram60xBusInit - initialize 60x Bus SDRAM.
*
* This routine initialize 60x Bus SDRAM.
*
* SYNOPSIS
* \ss
* void romMemcSdram60xBusInit
*     (
*     void
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romMemcSdram60xBusInit)
	mfspr	r29,LR

	/*
	 *    INIT 60x BUS
	 */

	/*
	 * CS2/CS3 to 60x Bus SRAM.
	 */
#ifdef INCLUDE_64MEG_SDRAM
        lis     r5, HIADJ(0xfc0028c0)   /* CS2 -> 64Meg @ 0x00000000 */
        addi    r5, r5, LO(0xfc0028c0)
        stw     r5, INIT_OR2(r4)

        lis     r5, HIADJ(0x00000041)
        addi    r5, r5, LO(0x00000041)
        stw     r5, INIT_BR2(r4)

        lis     r5, HIADJ(0x00000000)   /* CS3 Disabled */                       
        addi    r5, r5, LO(0x00000000)
        stw     r5, INIT_BR3(r4)
#endif /* INCLUDE_64MEG_SDRAM */

#ifdef INCLUDE_16MEG_SDRAM
	lis	r5, HIADJ(0xff000c80)   /* default 16Meg SIMM */ 
	addi	r5, r5, LO(0xff000c80)
	stw	r5, INIT_OR2(r4)
	
	lis	r5, HIADJ(0x00000041)
	addi	r5, r5, LO(0x00000041)
	stw	r5, INIT_BR2(r4)

	lis	r5, HIADJ(0xff000c80)
	addi	r5, r5, LO(0xff000c80)
	stw	r5, INIT_OR3(r4)

	lis	r5, HIADJ(0x01000041)
	addi	r5, r5, LO(0x01000041)
	stw	r5, INIT_BR3(r4)
#endif /* INCLUDE_16MEG_SDRAM */

	/* set the 60x bus-assigned SDRAM refresh timer */

	addi	r5,0,0x000e
	stb	r5, INIT_PSRT(r4)

	/*
	 * Initialize SDRAM.
	 */
#ifdef INCLUDE_64MEG_SDRAM
        lis     r5, HIADJ(0x294EB452)           /* Issue Precharge All-Banks command */
        addi    r5, r5, LO(0x294EB452)
        stw     r5, INIT_PSDMR(r4)
        
        addis   r0,0,0                          /* (write a 0xff to address 0) */
        addi    r5,0,0x00FF
        stb     r5,0(r0)

        lis     r5, HIADJ(0x094EB452)           /* Issue single CBR Refresh command */
        addi    r5, r5, LO(0x094EB452)
        stw     r5, INIT_PSDMR(r4)
        
        lis     r6, HIADJ(0x00000008)           
        addi    r6, r6, LO(0x00000008)
        mtspr   CTR,r6
        eieio
        sync

        addis   r0,0,0                                  
        addi    r5,0,0x00FF
        eieio
        sync

write_loop0:                                    /* Issue 8 0xFF writes to address 0 */ 
        stb     r5,0(r0)                                        
        addi    r0,0,1                          /* Increment address        */
        eieio
        sync
        bc      16,0,write_loop0
        lis     r5, HIADJ(0x194EB452)           /* Issue Mode Set command */
        addi    r5, r5, LO(0x194EB452)
        stw     r5, INIT_PSDMR(r4)
        
        addi    r5,0,0x00FF                     /* (write a 0xff to address 0) */
        stb     r5,0(r0)

        lis     r5, HIADJ(0x414EB452)           /* Issue Normal Operation command */
        addi    r5, r5, LO(0x414EB452)
        stw     r5, INIT_PSDMR(r4)                        
#endif /* INCLUDE_64MEG_SDRAM */

#ifdef INCLUDE_16MEG_SDRAM
	lis	r5, HIADJ(0x298EB452)
	addi	r5, r5, LO(0x298EB452)
	stw	r5, INIT_PSDMR(r4)
	
	addis	r0,0,0
	addi	r5,0,0x00FF
	stb	r5,0(r0)

	lis	r5, HIADJ(0x098EB452)
	addi	r5, r5, LO(0x098EB452)
	stw	r5, INIT_PSDMR(r4)
	
	lis	r6, HIADJ(0x00000008)
	addi	r6, r6, LO(0x00000008)
	mtspr	CTR,r6
	eieio
	sync

        addis   r0,0,0                                  
        addi    r5,0,0x00FF
        eieio
        sync

write_loop0:                                /* Issue 8 0xFF writes to address 0 */ 
        stb     r5,0(r0)                                        
        addi    r0,0,1                      /* Increment address        */
        eieio
        sync
        bc      16,0,write_loop0

	lis	r5, HIADJ(0x198EB452)
	addi	r5, r5, LO(0x198EB452)
	stw	r5, INIT_PSDMR(r4)
	
	addi	r5,0,0x00FF
	stb	r5,0(r0)

	lis	r5, HIADJ(0x418EB452)
	addi	r5, r5, LO(0x418EB452)
	stw	r5, INIT_PSDMR(r4)
#endif /* INCLUDE_16MEG_SDRAM */

	mtspr	LR,r29
	bclr	20,0
FUNC_END(romMemcSdram60xBusInit)

/***************************************************************************
*
* romMemcSdramLocalBusInit - initialize Local Bus SDRAM.
*
* This routine initialize 60x Bus SDRAM.
*
* SYNOPSIS
* \ss
* void romMemcSdramLocalBusInit
*     (
*     void
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romMemcSdramLocalBusInit)
	mfspr	r29,LR

	/*
	 *    INIT LOCAL BUS
	 */

	lis	r0, HIADJ(0x00000000)
	ori	r0, r0, LO(0x00000000)
	
	/*
	 * PROGRAM REFRESH 
	 */

	addi	r5,0,0x000E
	stb	r5,INIT_LSRT(r4)

	lis	r5, HIADJ(0xFFC01480)
	addi	r5, r5, LO(0xFFC01480)
	stw	r5, INIT_OR4(r4)

	lis	r5, HIADJ(0x04001861)
	addi	r5, r5, LO(0x04001861)
	stw	r5, INIT_BR4(r4)

	sync

	lis	r5, HIADJ(0x2886A552)
	addi	r5, r5, LO(0x2886A552)
	sync
	stw	r5, INIT_LSDMR(r4)

	lis	r2, HIADJ(0x04000000)
	addi	r2, r2, LO(0x04000000)

	lis	r6, HIADJ(0x04000000)
	addi	r6, r6, LO(0x04000000)
	sync

	stb	r6,0(r2)

	lis	r5, HIADJ(0x0886A552)
	addi	r5, r5, LO(0x0886A552)
	sync
	stw	r5, INIT_LSDMR(r4)

	/*
	 * Loop 8 times, writing 0 to address 0x04000000
	 */

	addis	r6,0,0
	ori	r6,r6,8
	mtspr	CTR,r6

	addi	r5,0,0

write_loop1:
	stw	r5,0(r2)

	bc	16,0,write_loop1

	lis	r5, HIADJ(0x1886A552)
	addi	r5, r5, LO(0x1886A552)
	sync
	stw	r5, INIT_LSDMR(r4)

	addis	r6,0,0
	stb	r6,0(r2)

	lis	r5, HIADJ(0x4086A552)
	addi	r5, r5, LO(0x4086A552)
	sync
	stw	r5, INIT_LSDMR(r4)

	mtspr	LR,r29
	bclr	20,0
FUNC_END(romMemcSdramLocalBusInit)

/***************************************************************************
*
* romCacheInit - minimum initialize of thecache
*
* This routine initialize of the cache.
*
* SYNOPSIS
* \ss
* void romCacheInit
*     (
*     void
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romCacheInit)

	/* turn off data and instruction cache */

	mfspr	r5, HID0
	isync
	rlwinm	r4, r5, 0, _PPC_HID0_BIT_DCE + 1, _PPC_HID0_BIT_ICE - 1
	                   /* r4 has enable bits cleared */
	sync
	isync
	mtspr	HID0, r4	/* HDI0 = r4 */
	isync

	/* invalidate the MPU's data/instruction caches */

	ori	r5, r5, _PPC_HID0_ICE | _PPC_HID0_DCE
		                 /* r5 has invalidate bits set */
	or	r4, r4, r5	 /* set bits */
	sync
	isync
	mtspr	HID0, r4	/* HID0 = r4 */
	andc	r4, r4, r5	/* clear bits */
	isync
	mtspr	HID0, r4
	isync

	/* turn the instruction cache ON for faster FLASH ROM boots */

	ori	r4, r4, _PPC_HID0_ICE | _PPC_HID0_ICFI	/* set ICE & ICFI */
	rlwinm	r5, r4, 0, _PPC_HID0_BIT_ICFI + 1, _PPC_HID0_BIT_ICFI - 1
				/* clear the ICFI bit */
	isync

	/*
	 * The setting of the instruction cache enable (ICE) bit must be
	 * preceded by an isync instruction to prevent the cache from being
	 * enabled or disabled while an instruction access is in progress.
	 */

	mtspr	HID0, r4	/* Enable Instr Cache & Inval cache */
	sync
	mtspr	HID0, r5	/* using 2 consec instructions */
				/* PPC603 recommendation */

	bclr	20,0
FUNC_END(romCacheInit)