rominit.s

wind river提供的MPC8260的BSP典型代码

/* romInit.s - SBC8260 ROM initialization module */

/* Copyright 1984-2001 Wind River Systems, Inc. */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01c,07may01,g_h  add include "wrSbc8260.h"
01b,18aug99,elk  fixed 60x bus SDRAM 16Mb problem.
01a,15mar99,elk  created from vads8260/romInit.s (ver 01k).
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "wrSbc8260.h"
#include "regs.h"
#include "sysLib.h"
#include "drv/timer/m8260Clock.h"
#include "drv/mem/m8260Siu.h"
#include "drv/mem/m8260Memc.h"	

	/* internals */

	FUNC_EXPORT(_romInit)	/* start of system code */
	FUNC_EXPORT(romInit)	/* start of system code */
	
	/* externals */

	FUNC_IMPORT(romStart)	/* system initialization routine */

        _WRS_TEXT_SEG_START

/***************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* SYNOPSIS
* \ss
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
* \se
*/

FUNC_BEGIN(_romInit)
FUNC_BEGIN(romInit)

	bl	cold		/* jump to the cold boot initialization */
        
        nop
	
	bl	start		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-2001 Wind River Systems, Inc."
	.align 2

cold:
	li	r3, BOOT_COLD	/* set cold boot as start type */
			
start:
	/* set the MSR register to a known state */

	xor	r4, r4, r4		/* clear register R4 */
	sync				/* synchronize */
	mtmsr 	r4			/* clear the MSR register */
	isync				/* synchronize */

	/* Turn off data and instruction cache control bits */
	
	mfspr	r7,HID0			/* r7 = HID0 */
	andi.	r7,r7,0xcfff		/* make sure lock bits are clear */
                                        /* r8 has ICE,DCE,ICI,DCI bits set */
	ori	r8,r7,(_PPC_HID0_ICE | _PPC_HID0_DCE | _PPC_HID0_ICFI | _PPC_HID0_DCFI)		
	andi.	r7,r7,0x03ff		/* r7 has enable bits cleared */
	sync
	mtspr	HID0,r8			/* HIDO = r8 */
	isync
	sync
	mtspr	HID0,r7			/* HIDO = r7 */
	isync

	/* Init the Segment registers */

	xor	r7,r7,r7
	isync
	mtsr    0,r7
	isync
	mtsr    1,r7
	isync
	mtsr    2,r7
	isync
	mtsr    3,r7
	isync
	mtsr    4,r7
	isync
	mtsr    5,r7
	isync
	mtsr    6,r7
	isync
	mtsr    7,r7
	isync
	mtsr    8,r7
	isync
	mtsr    9,r7
	isync
	mtsr    10,r7
	isync
	mtsr    11,r7
	isync
	mtsr    12,r7
	isync
	mtsr    13,r7
	isync
	mtsr    14,r7
	isync
	mtsr    15,r7
	isync

	mtspr	IBAT0U,r7		/* clear all upper BATS first */
	mtspr	IBAT1U,r7
	mtspr	IBAT2U,r7
	mtspr	IBAT3U,r7
	mtspr	DBAT0U,r7
	mtspr	DBAT1U,r7
	mtspr	DBAT2U,r7
	mtspr	DBAT3U,r7

	mtspr	IBAT0L,r7		/* then clear lower BATS */
	mtspr	IBAT1L,r7
	mtspr	IBAT2L,r7
	mtspr	IBAT3L,r7
	mtspr	DBAT0L,r7
	mtspr	DBAT1L,r7
	mtspr	DBAT2L,r7
	mtspr	DBAT3L,r7
	isync

	/* Zero-out SPRGs */

	mtspr   272,r7
	mtspr   273,r7
	mtspr   274,r7
	mtspr   275,r7

	/* invalidate entries within both TLBs */
	li	r7,128
	mtctr	r7		/* CTR = 32  */
	xor	r7,r7,r7	/* r7 = 0    */
	isync			/* context sync req'd before tlbie */
tlbloop:
	tlbie	r7
	addi	r7,r7,0x1000	/* increment bits 15-19 */
	sync			/* sync instr req'd after tlbie      */
	bdnz	tlbloop		/* decrement CTR, branch if CTR != 0 */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification.
	 */

	lis	r4, HIADJ(INTERNAL_MEM_MAP_ADDR+0x10000)
	addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR+0x10000)
	sync

	lis	r5, HIADJ(INTERNAL_MEM_MAP_ADDR)
	addi	r5, r5, LO(INTERNAL_MEM_MAP_ADDR)
	sync

	stw	r5, INIT_IMMR(r4)	/* initialize the IMMR register */

	/*
	 * initialize the SIU.
	 */

	bl	romSiuInit

	/*
	 * initialize the MEMC.
	 */

	bl	romMemcInit

	/*
	 * Initialize Instruction and Data Caches
	 */

	bl	romCacheInit

        /* initialize the stack pointer */

	lis	sp, HIADJ(STACK_ADRS)
	addi	sp, sp, LO(STACK_ADRS)
	

	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */


	/*
	 *	Set MPU/MSR to a known state
	 *	Turn on FP
	 */

	andi.	r7, r7, 0
	ori	r7, r7, _PPC_MSR_FP
	sync
	mtmsr 	r7
	isync

	/* Init the floating point control/status register */

	mtfsfi  7,0x0
	mtfsfi  6,0x0
	mtfsfi  5,0x0
	mtfsfi  4,0x0
	mtfsfi  3,0x0
	mtfsfi  2,0x0
	mtfsfi  1,0x0
	mtfsfi  0,0x0
	isync

	/* Initialize the floating point data regsiters to a known state */

	bl	ifpdr_value
	.long	0x3f800000	/* 1.0 */
ifpdr_value:
	mfspr	r7,8
	lfs	f0,0(r7)
	lfs	f1,0(r7)
	lfs	f2,0(r7)
	lfs	f3,0(r7)
	lfs	f4,0(r7)
	lfs	f5,0(r7)
	lfs	f6,0(r7)
	lfs	f7,0(r7)
	lfs	f8,0(r7)
	lfs	f9,0(r7)
	lfs	f10,0(r7)
	lfs	f11,0(r7)
	lfs	f12,0(r7)
	lfs	f13,0(r7)
	lfs	f14,0(r7)
	lfs	f15,0(r7)
	lfs	f16,0(r7)
	lfs	f17,0(r7)
	lfs	f18,0(r7)
	lfs	f19,0(r7)
	lfs	f20,0(r7)
	lfs	f21,0(r7)
	lfs	f22,0(r7)
	lfs	f23,0(r7)
	lfs	f24,0(r7)
	lfs	f25,0(r7)
	lfs	f26,0(r7)
	lfs	f27,0(r7)
	lfs	f28,0(r7)
	lfs	f29,0(r7)
	lfs	f30,0(r7)
	lfs	f31,0(r7)
	sync

        /*
         *     Set MPU/MSR to a known state
         *     Turn off FP
         */

        andi.  r7,r7,0
        sync
        mtmsr  r7
        isync

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart	= R6
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: R6 - R7 + R8 
	 */

        lis	r6, HIADJ(romStart)	
        addi	r6, r6, LO(romStart)	/* load R6 with C entry point */

	lis	r7, HIADJ(romInit)
	addi	r7, r7, LO(romInit)

	lis	r8, HIADJ(ROM_TEXT_ADRS)
	addi	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */

	mtlr	r6			/* move C entry point to LR */
	blr				/* jump to the C entry point */
FUNC_END(romInit)
FUNC_END(_romInit)

/***************************************************************************
*
* romSiuInit - initialize the general SIU
*
* This routine initialize the System Interfac Unit
*
* SYNOPSIS
* \ss
* void romSiuInit
*     (
*     void
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romSiuInit)

	/* BCR */

	lis     r5, HIADJ(0x10000000)
	addi	r5, r5, LO(0x10000000)
	stw	r5, INIT_BCR(r4)

	/* PPC_ACR */
	
	lis	r5, HIADJ(0x00000002)
	addi	r5, r5, LO(0x00000002)
	stb	r5, INIT_PPC_ACR(r4)

	/* PPC_ALRH */
	
	lis	r5, HIADJ(0x01234567)
	addi	r5, r5, LO(0x01234567)
	stw	r5, INIT_PPC_ALRH(r4)

	/* SYPCR */
	
	lis	r5, HIADJ(0xffffffc3)
	addi	r5, r5, LO(0xffffffc3)
	stw	r5, INIT_SYPCR(r4)

	/* SIUMCR */
	
	lis	r5, HIADJ(0x0e240000)
	addi	r5, r5, LO(0x0e240000)
	stw	r5, INIT_SIUMCR(r4)

	/* TESCR1 */
	
	lis	r5, HIADJ(0x00004000)
	addi	r5, r5, LO(0x00004000)
	stw	r5, INIT_TESCR1(r4)

	/* LTESCR1 */

	lis	r5, HIADJ(0x00004000)
	addi	r5, r5, LO(0x00004000)
	stw	r5, INIT_LTESCR1(r4)

	/* SCCR */
	
	lis	r5, HIADJ(0x00000001)
	addi	r5, r5, LO(0x00000001)
	stw	r5, INIT_SCCR(r4)

	/* set the memory periodic timer prescaler */

	li    r5,0x4000    /* Set prescaler for 66 Mhz input clk */
	lis   r6,HIADJ(HRDW_CONFIG_BYTE4)
	lbz   r6,LO(HRDW_CONFIG_BYTE4)(r6)
	cmpwi r6, 5        /* is MODCK_H 5 or more ? */
        bge   setPrescaler /* if so, input clk is 66 Mhz */
	li    r5,0x2000    /* else, set prescaler for 33 Mhz input clk */

setPrescaler:
         sth   r5,INIT_MPTPR(r4)
	bclr   20,0
FUNC_END(romSiuInit)

/***************************************************************************
*
* romMemcInit - initialize the memory controller and SDRAM
*
* This routine initialize the memory controller and SDRAM
*
* SYNOPSIS
* \ss
* void romMemcInit
*     (
*     void
*     )