target.nr

wind river提供的MPC8260的BSP典型代码

.CE
TO:
.CS
    /* Specify CS0 connection: ON_BOARD_FLASH, SIMM_FLASH */
    #define BOOT_FLASH SIMM_FLASH
.CE

New boot ROM must be burned, and a new image must be built.

**Note: You need also to change the jumpers and switch's configuration. For 
        more details see "Setting the board Jumpers & Switches" section in 
        this file.

.SS "Switching between the FCC to SCC"
The BSP is using by default the FCC channel for booting, but it also include
the SCC interface, and you can choose between them in the boot prompt. There 
is also an option to include the only one of the interfaces. Please follow 
those steps to get the BSP working only with the SCC or FCC driver instead of 
working with both of them:

1. In "config.h" change the following lines:

FROM:
.CS
#define BOOT_DEVICE SCC_FCC_END
.CE

TO for Only the SCC Channel:
.CS
#define BOOT_DEVICE SCC_END
.CE
OR TO for Only the FCC Channels:
.CS
#define BOOT_DEVICE FCC_END
.CE

2. In the makefile change the following lines:

FROM:
.CS
MACH_EXTRA    = m8260SccEnd.obj
.CE
TO for Only the FCC Channels:
.CS
MACH_EXTRA    = #m8260SccEnd.obj
.CE

3. Now rebuild the bootrom and create a new VxWorks image project and build it.

** Don't forget to change the device name to "motscc" in the "boot device" line 
in the bootrom if you want to use the SCC channel.

.SS "Serial Configuration"
SMC1 and SMC2 are configured as UART devices with 8 data bits, 1 stop bit, 
hardware handshaking, and parity disabled.

.SS "Serial Connections"
This VxWorks MPC8260 BSP uses a simple 3 wire connection and standard RJ11 
where pin 1 = RIN, pin 2 = TOUT, pin 3 = NC, and pin 4 = GND.

.SS "SCSI Configuration"
There is no SCSI interface on this board.

.SS "Network Configuration"
SCC1 is configured as a 10Mb/s Ethernet port
FCC2 is configured as a 10/100Mb/s Fast Ethernet port

.SS "VME Access"
NA

.SS "PCI Access"
There is PCI interface on this board, but the current version of the CPU is not 
supporting PCI interface, also the BSP dosn't support PCI.

.SS "Force Default Boot Line Option"
If the FORCE_DEFAULT_BOOT_LINE is defined (in config.h), then the 
DEFAULT_BOOT_LINE parameters are used as boot parameters regardless of the 
NVRAM values previously specified. Recall, boot parameters are stored in the 
NVRAM device so boot parameters are not lost during a power cycle.
  
Defining the FORCE_DEFAULT_BOOT_LINE value is useful for debugging 
visionICE II/visionPROBE II downloaded  RAM based vxWorks images.  It is 
considered a DEBUG options so it should be #undef'ed for the final image.

Normally the boot parameters are specified at the bootrom prompt and stored in 
NVRAM.When a downloaded image executes, the boot parameters are retrieved from 
the NVRAM device.  
  
This can sometimes cause undesired results. For example, if the NVRAM has been  
previously initialized, then changing the DEFAULT_BOOT_LINE in the "config.h" 
will not result in the new settings being used. The reason being is the 
initialization code always takes the boot parameters from the NVRAM device. If 
there are sane values in the NVRAM device, these boot parameters are used.

If you intended to debug an image by downloading with WR's visionTools
and plan on changing the DEFAULT_BOOT_LINE parameters a number of times,
it might be convenience to define this FORCE_DEFAULT_BOOT_LINE parameter.

As a note, unitialized NVRAM device is initialized automatically with
the DEFAULT_BOOT_LINE parameters specified in the "config.h" file.

As an alternate solution for the above scenario, the boot parameters can
be changed via the bootrom. This will store the values in NVRAM and
will subsequentially be used by the download image.  This would require
a sane bootrom and would require the target board to run via the bootroms
to set the values and then halted to download the image to be debugged via
the WR Tools.

.SS "Using the Local Bus"
If a you configures SCC or FCC use of local bus, or is building a ROM 
resident image, then you MUST define INCLUDE_LOCAL_BUS_SDRAM in "config.h" 
as follow:

FROM:
.CS
   #undef INCLUDE_LOCAL_BUS_SDRAM
.CE

TO:
.CS
   #define INCLUDE_LOCAL_BUS_SDRAM
.CE


.SS "ROM Resident Considerations"
Before you build a rom resident vxWorks image you need to modify the following 
parameter in "config.h" :

FROM:
.CS 
    #undef FORCE_DEFAULT_BOOT_LINE
.CE

TO:
.CS 
    #define FORCE_DEFAULT_BOOT_LINE
.CE

Don't forget to enter the correct target IP address in the DEFAULT_BOOT_LINE. 
For more details please read the "Force Default Boot Line Option" section.

And in "wrSbc8260.h" to define the macro "#define INCLUDE_LOCAL_BUS_SDRAM".

** With the ROM RESIDENT from the user level, Zero Copy sockets is available, 
   but the driver will internally and transparently convert the transmit calls 
   to copy sends. 

.SS "ROM Considerations"
bootrom_uncmp.hex is provided with this BSP. The bootrom is configured to 
a ROM base address of 0x0. When programing the bootrom to the FLASH an offset
of 0xFFF00100 need to be given, also it's configured to use the 2 MByte On 
Board Flash ROM and FCC2 10/100BaseT Ethernet as default boot device and SMC1 
as console device. The hard reset configuration word must be programmed 
separately at the flash base address of 0xFE000000 and at offsets 0x0, 0x8, 
0x10, 0x18 and 0x20, see chapter 5 Reset in the MPC8260 PowerQUICC II User's 
Manual.

.SS "Delivered Objects"
The following images are delivered with the wrSbc8260 BSP:

.IP
bootrom_uncmp
.IP
bootrom_uncmp.hex
.IP
bootrom
.IP
bootrom.hex
.IP
vxWorks
.IP
vxWorks.st
.IP
m8260SccEnd.obj
.LP

.SS "Make Targets"
Only bootrom_uncmp, bootrom, bootrom_res, vxWorks, vxWorks_romResident have 
been tested.

.SS "Dual Port RAM Map"
The wrSbc8260 is using the m82xxDpramLib.c to allocate dynamically the 
necessary DPRAM memory for the serial and Ethernet channels. Key features of 
sysDpramLib are:

    - Init the DPRAM memory with considerations of any Microcode that add been
      loaded.
    
    - Allocate aligned and non aligned memory.
 
    - Free memory.

    - Manage a special section (b000 - c000) for special FCC needs.

    - Manage a special section (8000 - 9000) for special SCC needs.

.SS "Interrupts"
.LP
The following table describes the relationship between the interrupt
number, interrupt vector, and the interrupt bit position in the SIU
Interrupt Mask Register (SIMR_H and SIMR_L). Also described is the
mask to use to enable all interrupts of a higher priority.
.TS 
center;
c c c c c s c
c c c c c s c
c c c c c c c
nw(.3i) n n n n n l.
Default				Mask to Enable
Interrupt	Interrupt	Interrupt	SIMR	Higher Priority Interrupts	Interrupt
Priority	Number	Vector	Mask	SIMR_H	SIMR_L	Source
_
						HIGHEST PRIORITY
1	16	0x10	H 0x00000004	0000_0000	0000_0000	TMCNT
2	16	0x10	H 0x00000004	0000_0000	0000_0000	TMCNT
3	17	0x11	H 0x00000002	0000_0004	0000_0000	PIT
4	reserved
5	19	0x13	H 0x00004000	0000_0006	0000_0000	IRQ1
6	27	0x20	L 0x80000000	0000_4006	0000_0000	FCC1
7	28	0x21	L 0x40000000	0000_4006	8000_0000	FCC2
8	29	0x22	L 0x20000000	0000_4006	C000_0000	FCC3
9	inactive
10	unused
11	31	0x24	L 0x08000000	0000_4006	E000_0000	MCC1
12	32	0x25	L 0x04000000	0000_4006	E800_0000	MCC2
13	inactive
14	inactive
15	20	0x13	H 0x00002000	0000_4006	EC00_0000	IRQ2
16	21	0x14	H 0x00001000	0000_6006	EC00_0000	IRQ3
17	22	0x15	H 0x00000800	0000_7006	EC00_0000	IRQ4
18	23	0x16	H 0x00000400	0000_7806	EC00_0000	IRQ5
19	unused
20	35	0x28	L 0x00800000	0000_7C06	EC00_0000	SCC1
21	36	0x29	L 0x00400000	0000_7C06	EC80_0000	SCC2
22	37	0x2A	L 0x00200000	0000_7C06	ECC0_0000	SCC3
23	38	0x2B	L 0x00100000	0000_7C06	ECE0_0000	SCC4
24	inactive
25	inactive
26	inactive
27	inactive
28	unused
29	40	0x30	H 0x00010000	0000_7C06	ECF0_0000	PC15
30	12	0x0C	L 0x00000010	0001_7C06	ECF0_0000	Timer 1
31	41	0x31	H 0x00020000	0001_7C06	ECF0_0010	PC14
32	unused
33	42	0x32	H 0x00040000	0003_7C06	ECF0_0010	PC13
34	10	0x0A	L 0x00000040	0007_7C06	ECF0_0010	SDMA Bus Error
35	6	0x06	L 0x00000400	0007_7C06	ECF0_0050	IDMA1
36	unused
37	43	0x33	H 0x00080000	0007_7C06	ECF0_0450	PC12
38	44	0x34	H 0x00100000	000F_7C06	ECF0_0450	PC11
39	7	0x07	L 0x00000200	001F_7C06	ECF0_0450	IDMA2
40	13	0x0D	L 0x00000008	001F_7C06	ECF0_0650	Timer 2
.TE
.bp
.LP
Interrupts, continued:
.sp 3
.TS
center;
c c c c c s c
c c c c c s c
c c c c c c c
nw(.3i) n n n n n l.
Default				Mask to Enable
Interrupt	Interrupt	Interrupt	SIMR	Higher Priority Interrupts	Interrupt
Priority	Number	Vector	Mask	SIMR_H	SIMR_L	Source
_
						HIGHEST PRIORITY
41	45	0x35	H 0x00200000	001F_7C06	ECF0_0658	PC10
42	unused
43	unused
44	3	0x03	L 0x00002000	003F_7C06	ECF0_0658	RISC Timer Table
45	1	0x01	L 0x00008000	003F_7C06	ECF0_2658	I2C
46	unused
47	46	0x36	H 0x00400000	003F_7C06	ECF0_A658	PC9
48	47	0x37	H 0x00800000	007F_7C06	ECF0_A658	PC8
49	24	0x18	H 0x00000200	00FF_7C06	ECF0_A658	IRQ6
50	8	0x08	L 0x00000100	00FF_7E06	ECF0_A658	IDMA3
51	25	0x19	H 0x00000100	00FF_7E06	ECF0_A758	IRQ7
52	14	0x0E	L 0x00000004	00FF_7F06	ECF0_A758	Timer 3
53	unused
54	unused
55	48	0x38	H 0x01000000	00FF_7F06	ECF0_A75C	PC7
56	49	0x39	H 0x02000000	01FF_7F06	ECF0_A75C	PC6
57	50	0x3A	H 0x04000000	03FF_7F06	ECF0_A75C	PC5
58	15	0x0F	L 0x00000002	07FF_7F06	ECF0_A75C	Timer 4
59	unused
60	51	0x3B	H 0x08000000	07FF_7F06	ECF0_A75E	PC4
61	unused
62	9	0x09	L 0x00000080	0FFF_7F06	ECF0_A75E	IDMA4
63	2	0x02	L 0x00004000	0FFF_7F06	ECF0_A7DE	SPI
64	52	0x3C	H 0x10000000	0FFF_7F06	ECF0_E7DE	PC3
65	53	0x3D	H 0x20000000	1FFF_7F06	ECF0_E7DE	PC2
66	4	0x04	L 0x00001000	3FFF_7F06	ECF0_E7DE	SMC1
67	unused
68	5	0x05	L 0x00000800	3FFF_7F06	ECF0_F7DE	SMC2
69	54	0x3E	H 0x40000000	3FFF_7F06	ECF0_FFDE	PC1
70	55	0x3F	H 0x80000000	7FFF_7F06	ECF0_FFDE	PC0
71	unused
72	unused
73	reserved
						LOWEST PRIORITY

.TE

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information that the user needs
to know about the BSP.

.SS "Cache coherency between the 603 core and the CPM"
The MPC8260 is not maintaining cache coherency between the 603 core and the 
CPM, in result of this, all the data that is transfer from the 603 to the CPM 
an vise versa should be placed in non-cacheable memory. For example the FCC and 
SCC buffers and buffer descriptors should be allocated using cacheDmaMalloc(). 
In this BSP the BD are located inside the CPM DPRAM, that means only the 
buffers are on the 60x bus, and they are non-cacheable.

.SS "Known Problems"

.PP
If both the MOT_SCC_END and MOT_FCC_END driver are installed, the CPM Driver 
must be installed in endDevTbl[] first. This is a bug and probably has 
something to do with port pin set up order.

.PP
MAC Address not being displayed properly from ifShow().

.SH "BIBLIOGRAPHY"

.iB "Embedded Support Tools SBC8260 Hardware Reference Manual"
.iB "MPC8260 PowerQUICC II User's Manual MPC8260UM/D"
.iB "PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors MPCFPE32B/AD"
.iB "MPC603e & EC603e RISC Microprocessors User's Manual MPC603EUM/AD"