target.nr

wind river提供的MPC8260的BSP典型代码

.SS "Programming the Hard Reset Configuration Word to the On Board/SIMM FLASH"
.PP

1. Power off the SBC8260 board and set dip switch S2-1 to Open position 
   (Sets Reset Configuration to internal default).

2. Verify JP-24 jumper is set to 1-3 and 2-4 if you boot from the Local Flash.

3. Power on the SBC8260 and the emulator (visionPROBE II or visionICE II).

4. If you are using visionCLICK follow section 4.1, if you are using SingleStep 
   for vision follow section 4.2 :

   4.1 Using visionCLICK:

       4.1.1 In the terminal window at the ">BKM>" or ">ERR>" prompt enter the 
             "IN" command and press enter. Now you should get the ">BKM>" 
             prompt.

       4.1.2 Continue to step 5.

   4.2 Using SingleStep for vision:

       4.2.1 Go to the "File" menu and choose the "Start Debug Session..." .

       4.2.2 The "Debug" dialog box will popup, In the "Connection" tab
             choose the visionPROBE option & the correct LPT port if you 
             are using visionPROBE, or visionICE & enter the emulator IP 
             address if you are using visionICE.
			  
       4.2.3 In the "Processor" tab choose the MPC8260.

       4.2.4 In the "File" tab choose the "Debug without a file" option
             and press OK.

       4.2.5 Now should get the "Debug Status" dialogbox and in the 
             "Debug Session" field you should have in green 
             "Started Successfully", press the 'Close' button.

       4.2.6 Now go to the "Command" button in the toolbar and press on it. The
             "Command" Window will popup, the prompt in the window will be 
             "SingleStep". Bring the mouse cursor above the "Command" window 
             and press the right button. A menu will popup, choose the 
             "VisionShell(vsh)" option. Now the prompt in the window will be 
             ">BKM>".

       4.2.8 Cotinue to step 5.

5. At the ">BKM>" prompt enter: 

   If you are using the 2MB On Board FLASH: AMD 29F016B (2048 x 8) 1 Device,
   (8 Bit).

.CS	
   66Mhz Ocilator                33Mhz Ocilator
   --------------                --------------

   SY RSTCONF 04320205 8         SY RSTCONF 04320201 8
.CE

   If you are using the 4MB SIMM FLASH: AMD 29F080B (1024 x 8) 4 Device,
   (32 Bit).

.CS
   66Mhz Ocilator                33Mhz Ocilator
   --------------                --------------

   SY RSTCONF 0C320205 32        SY RSTCONF 0C320201 32
.CE

   The emulator should respond with the following:

.CS
   + Flash Erase : Success
   + Program Configuration Word : Success
   >BKM>
.CE

6. Power off the SBC8260 and close switch S2-1. You will get the ">ERR>" 
   prompt in visionCLICK "Terminal" window or in SingleStep "Command" window.

7. Power on the SBC8260 and at the ">ERR>" prompt enter: "IN"

8. The SBC8260 will read the configuration word from Flash during reset and 
   initialize the processor base on the configuration word entered in step 5 
   and you will get to ">BKM>".

9. Now you are ready to disconnect the emulator and run the BSP.


.SS "Changing Core Speed / Cpm Speed / Input Xtal Speed"
.PP
In order to use the 66Mhz Ocilator instead of th 33Mhz you need to follow 
those steps:

    1. Power off the SBC8260 board and set dip switch S2-1 to Open posetion 
       (Sets Reset Configuration to internal default).

   2. Change the following switches:

       _________________________________
      | 66Mhz Ocilator | 33Mhz Ocilator |
      |----------------|----------------|
      |   S2-6 Open    |   S2-6 Close   |
      |   S2-7 Open    |   S2-7 Open    |
      |   S2-8 Open    |   S2-8 Close   |
      |________________|________________|

       The BSP have the option to determine the CPU's Core Speed, the speed 
       at which to run the CPM, and the Input Xtal Speed Automatically by 
       reading the user switch. The BSP can also be configured to determine 
       this information Manually.

       2.1 In order to determine the speed manually follow those steps:
	
           2.1.1 In "config.h" define the following parameter:
	
	         From:
                  
                 .CS	   
	         #undef  HARDCODED_FREQ_PARMS
                 .CE	   

                 To:
                  
                 .CS
                 #define HARDCODED_FREQ_PARMS
                 .CE

           2.1.2 With this #define'd, the INPUT_FREQUENCY, CPM_FREQUENCY, and 
                 CORE_FREQUENCY "config.h" parameters must also be defined:

                 .CS
                 #define  INPUT_FREQUENCY FREQ_66MHZ  
                 #define  CPM_FREQUENCY   FREQ_133MHZ
                 #define  CORE_FREQUENCY  FREQ_200MHZ	
                 .CE

                 Note(S): 8260 devices are marked: XPC[MPC]8260xxx core 
                          speed/cpm speed/clock speed. In this example, the 
                          chip was marked as 200/133/66Mhz. The board had a 
                          66Mhz Oscillator as a clock. Also in this case, the 
                          core is run at 200.

                          Each time "config.h" is edited, new vxWorks and 
                          bootrom images should be built and Flash memory is 
                          to be programmed.

       2.2 In order to determine the speed automatically follow those steps:
	
           2.2.1. In "config.h" undefine the following parameter:

                  .CS	   
                  #undef  HARDCODED_FREQ_PARMS
                  .CE	   

           2.2.2 Set the following switches:

                  _________________________________
                 | 66Mhz Ocilator | 33Mhz Ocilator |
                 |----------------|----------------|
                 |   S6-6 Open    |   S6-6 Close   |
                 |   S6-7 Open    |   S6-7 Open    |
                 |   S6-8 Open    |   S6-8 Close   |
                 |________________|________________|


                 Note: In this case, the INPUT_FREQUENCY, CPM_FREQUENCY, and 
                       CORE_FREQUENCY defines are ignored, and the User Dip 
                       Switch positions S6-6, S6-7, and S6-8 are used to 
                       determine the MODCK[1-3] bits. User Dip switches S6-6, 
                       S6-7, and S6-8 should be set to the same positions as 
                       the Configuration Dip Switch positions S2-6, S2-7, and 
                       S2-8. The reason this is needed is because S2 cannot be 
                       read by software and the reset state of the Mod Clock 
                       Bits cannot be read by software. 

   3. Now please go to the section above:
	
      "Programming the Hard Reset Configuration Word to the On Board/SIMM FLASH"
       and follow the instructions on how to program the new Hardware Reset 
       Configuration Word that will match your setting.

.SS "SDRAM Size"
.PP
Initial boards and bsps were supplied with a 16Meg SDRAM
SIMM; more recent evaluation boards are supplied with a 64Meg SIMM.
the BSP is logically setup for 64Meg of SDRAM. The 64Meg is divided 
into two halves. The first 32Meg is useable for code and data. 
The second 32Meg is specified as USER_RESERVED_MEM memory. The 64Meg 
option is specified as a #define in the "config.h" file. If your 
board comes with 16Meg of SDRAM change the following macro in "config.h".
From:
.CS
    #undef  INCLUDE_16MEG_SDRAM			    
    #define INCLUDE_64MEG_SDRAM	    /* (requires hardware modification) */
.CE
To:
.CS
    #define INCLUDE_16MEG_SDRAM			    
    #undef  INCLUDE_64MEG_SDRAM	    /* (requires hardware modification) */
.CE
The reason the BSP divides the 64Meg SDRAM into two 32Meg sections has 
to do with the EABI compilation option of a 24 bit address. The default
compilation options generates a "bl" for branch instructions. This 
increases performance, but places a 32Meg address limit on the code.
  
There are two "work arounds" to this limitation.
 
    1.) recompile all the source with the -mlongcall compilation flag
    2.) add remaining 32Meg to the memory pool vi the memAddToPool() function.
  
Option #1 would require all the libraries, driver, and the BSP to be 
recompiled with the -mlongcall compiler option. This results in a number
of code changes; the most obvious code change is branches are implemented
via brlr instruction verses the bl instruction.
  
Option #2, the perferrable options, requires the USER_RESERVED_MEM and the
memAddToPool() constructs be used to specify the remaining 32Meg to be added
to the memory pool. Consult WindTech Note WTN41 for details on specifying
user memory.

** Note: Don't forget to change the "RAM_HIGH_ADRS" value in the makefile to be
         the same as in "config.h". For 16Meg "00E00000" and for 64Meg 
         "01E00000".

.SS "Ethernet Ports"
The Fast Ethernet Controller (FCC) makes available fast Ethernet connectivity
through the use of a 10/100BaseT Ethernet transceiver connected to the MII port 
(JP21). SCC is also available.
Both FCC2 and SCC1 are configured by the BSP as Ethernet ports.
The name "motfcc" should be specified to the boot ROM as the boot device when 
booting vxWorks over the FCC2 interface.
The name "motscc" should be specified to the boot ROM as the boot device when 
booting vxWorks over the SCC1 interface.
Both devices are configured to use END-style network drivers.
You may prevent the configuration and initialization of either of these ports
by modifying the macro #define BOOT_DEVICE SCC_FCC_END in config.h to be:

.CS
    #define BOOT_DEVICE SCC_FCC_END	/@ initialize both ports @/
    	or
    #define BOOT_DEVICE FCC_END		/@ initialize FCC2 @/
    	or
    #define BOOT_DEVICE SCC_END		/@ initialize SCC1 @/
.CE

Each time config.h is edited, new vxWorks and bootrom images must be built 
and Flash memory must be reprogrammed.

.SS "NVRAM Support" 
This BSP implements NvRam via a EEPROM device. There are a few user parameters 
associated with this device. The parameters are located in the "config.h" 
file and are:

.CS  
    #undef  INCLUDE_EEPROM_LOCKING
    #define SMART_EEPROM_WRITE
    #define ETHERNET_ADR_SET /* (used in bootConfig.c to enable 'N' command) */
.CE

The INCLUDE_EEPROM_LOCKING parameter is typically #undef'ed. If #define'ed, the
EEPROM will be software locked between accesses. This was implemented on the
BSP to work around a power-on EEPROM corruption problem. It should be noted, 
that if the EEPROM is locked, its contents can not be altered via an emulator 
or visionPROBE II or visionICE II (JTAG does not meet the minimum timing 
relationships needed).

The SMART_EEPROM_WRITE parameter is typically #define'd. When defined, the 
EEPROM write code first checks to see if a cell is the desired value. If the 
memory location already contains the desired value, the write is skipped. This 
was implemented to increase the life of the EEPROM device.
  
The ETHERNET_ADR_SET is a value that indicates the MAC address is stored in 
NVRAM and alterable via the 'N' bootrom command.

.SS "Changing the Ethernet Address"
The SBC8260 boards do not have a unique Ethernet hardware address 
assigned to each board. A unique address is absolutely necessary if the
user wishes to connect the board to a network. Thus, the user must 
provide a suitable 6 byte Ethernet address for each board used
on a network. The default Ethernet Address is specified in the "config.h"
The following relate to the storage of the Ethernet address in NVRAM:

.CS
    /* Ethernet MAC Address Parameters */
    #define CUST_ENET3 0x01 /* Customer specific portion of MAC address */
    #define CUST_ENET4 0x02
    #define CUST_ENET5 0x03
.CE

The first three bytes (0x00, 0xa0, 0x1e) are a Wind River specific prefix
that should be kept as-is. If for some reason you need to change them, in
"config.h" change the following macros:

.CS
    #define WR_ENET0  0x00  /* Wind River specific portion of MAC (MSB->LSB) */
    #define WR_ENET1  0xa0
    #define WR_ENET2  0x1e	  

    #define	ENET_DEFAULT 0xa01e0000
.CE

Note:
    The "ENET_DEFAULT" macro should contain the same number as the three 
    "WR_ENETx" macros. For example : 

.CS
    #define WR_ENET0  0x11
    #define WR_ENET1  0x22
    #define WR_ENET2  0x33	  

    #define	ENET_DEFAULT 0x11223300
.CE

The user must change the last three bytes from 0x03, 0x02, 0x01 to three 
unique bytes (i.e., bytes not used by any other Wind River Ethernet 
connection on your net). Check with your system administrator if you 
do not know this information. If these bytes need changing (they often will 
not), a new boot ROM must be burned, and a new image must be built.
Ethernet Address can be specified at the bootrom prompt (N command). The 
Ethernet address is stored in the on board NVRAM. This option will able you to 
change the last three bytes. To use this option, open the console window (for 
example: hayper terminal) and when the bootrom banner appear and the countdown 
start, press any key, when you get the [VxWorks Boot] prompt , press 'N' and 
follow the instructions.

.SS "BOOT FLASH"
The BSP configures to use the 2MByte Local Flash. In order to use the 4MByte 
SIMM Flash instead , change in "config.h" the following lines:

FROM: 
.CS
    /* Specify CS0 connection: ON_BOARD_FLASH, SIMM_FLASH */
    #define BOOT_FLASH ON_BOARD_FLASH