📄 datapage.lst
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000e 9630 [3] LDAA 48
849: PSHA
0010 36 [2] PSHA
850: loop:
851: STAB PAGE_ADDR ;// set source page
0011 5b30 [2] STAB 48
852: LDAA 1,X+ ;// load value
0013 a630 [3] LDAA 1,X+
853: MOVB 4,SP, PAGE_ADDR ;// set destination page
0015 180d840030 [5] MOVB 4,SP,48
854: STAA 1,Y+
001a 6a70 [2] STAA 1,Y+
855: CPX 1,SP
001c ae81 [3] CPX 1,SP
856: BNE loop
001e 26f1 [3/1] BNE *-13 ;abs = 0011
857:
858: LDAA 5,SP+ ;// restore old page value and release stack
0020 a6b4 [3] LDAA 5,SP+
859: STAA PAGE_ADDR ;// store it into page register
0022 5a30 [2] STAA 48
860: _SRET ;// debug info only: This is the last instr of a function with a special return
861: RTS
0024 3d [5] RTS
862: }
863: #endif
864: }
865:
866: /*--------------------------- _FAR_COPY --------------------------------
867:
868: The _FAR_COPY runtime routine was used to copied large memory blocks in previous compiler releases.
869: However this release now does use _FAR_COPY_RC instead. The only difference is how the size of
870: the area to be copied is passed into the function. For _FAR_COPY the size is passed on the stack just
871: above the return address. _FAR_COPY_RC does expect the return address just after the JSR _FAR_COPY_RC call
872: in the code of the caller. This allows for denser code calling _FAR_COPY_RC but does also need a slightly
873: larger runtime routine and it is slightly slower.
874: The _FAR_COPY routine is here now mainly for compatibility with previous releases.
875: The current compiler does not use it.
876:
877: --------------------------- _FAR_COPY ----------------------------------*/
878:
879: #ifdef __cplusplus
880: extern "C"
881: #endif
882: #pragma NO_ENTRY
883: #pragma NO_EXIT
884: #pragma NO_FRAME
885:
886: void NEAR _FAR_COPY(void) {
Function: _FAR_COPY
Source : D:\Chg\Tech\FSL_Support\from ChatRoom\9S12DP256_Vector Remapping_Jul262006\Sources\datapage.c
Options : -CPUHCS12 -D__NO_FLOAT__ -Env"GENPATH=D:\Chg\Tech\FSL_Support\from ChatRoom\9S12DP256_Vector Remapping_Jul262006;D:\Chg\Tech\FSL_Support\from ChatRoom\9S12DP256_Vector Remapping_Jul262006\bin;D:\Chg\Tech\FSL_Support\from ChatRoom\9S12DP256_Vector Remapping_Jul262006\prm;D:\Chg\Tech\FSL_Support\from ChatRoom\9S12DP256_Vector Remapping_Jul262006\cmd;D:\Chg\Tech\FSL_Support\from ChatRoom\9S12DP256_Vector Remapping_Jul262006\Sources;D:\Program Files\Freescale\CW for HC12 V4.5\lib\HC12c\lib;D:\Program Files\Freescale\CW for HC12 V4.5\lib\HC12c\src;D:\Program Files\Freescale\CW for HC12 V4.5\lib\HC12c\include" -Env"LIBPATH=D:\Program Files\Freescale\CW for HC12 V4.5\lib\HC12c\include" -Env"OBJPATH=D:\Chg\Tech\FSL_Support\from ChatRoom\9S12DP256_Vector Remapping_Jul262006\bin" -Env"TEXTPATH=D:\Chg\Tech\FSL_Support\from ChatRoom\9S12DP256_Vector Remapping_Jul262006\bin" -Lasm=%n.lst -Mb -ObjN="D:\Chg\Tech\FSL_Support\from ChatRoom\9S12DP256_Vector Remapping_Jul262006\9S12DP256_Vector_Remapping_Jul262006_Data\Full_Chip_Simulation\ObjectCode\datapage.c.o"
887: #if USE_SEVERAL_PAGES
888: __asm {
889: DEX ;// source addr-=1, because loop counter ends at 1
890: PSHX ;// save source offset
891: PSHD ;// save both pages
892: DEY ;// destination addr-=1, because loop counter ends at 1
893: PSHY ;// save destination offset
894: LDX 8,SP ;// load counter, assuming counter > 0
895:
896: loop:
897: LDD 4,SP ;// load source offset
898: LEAY D,X ;// calculate actual source address
899: LDAB 2,SP ;// load source page
900: __PIC_JSR(_LOAD_FAR_8) ;// load 1 source byte
901: PSHB ;// save value
902: LDD 0+1,SP ;// load destination offset
903: LEAY D,X ;// calculate actual destination address
904: PULA ;// restore value
905: LDAB 3,SP ;// load destination page
906: __PIC_JSR(_STORE_FAR_8) ;// store one byte
907: DEX
908: BNE loop
909: LDX 6,SP ;// load return address
910: LEAS 10,SP ;// release stack
911: JMP 0,X ;// return
912: }
913: #else
914: __asm {
915: PSHD ;// store page registers
0000 3b [2] PSHD
916: TFR X,D
0001 b754 [1] TFR X,D
917: ADDD 4,SP ;// calculate source end address
0003 e384 [3] ADDD 4,SP
918: STD 4,SP
0005 6c84 [2] STD 4,SP
919: PULB ;// reload source page
0007 33 [3] PULB
920: LDAA PAGE_ADDR ;// save page register
0008 9630 [3] LDAA 48
921: PSHA
000a 36 [2] PSHA
922: loop:
923: STAB PAGE_ADDR ;// set source page
000b 5b30 [2] STAB 48
924: LDAA 1,X+ ;// load value
000d a630 [3] LDAA 1,X+
925: MOVB 1,SP, PAGE_ADDR ;// set destination page
000f 180d810030 [5] MOVB 1,SP,48
926: STAA 1,Y+
0014 6a70 [2] STAA 1,Y+
927: CPX 4,SP
0016 ae84 [3] CPX 4,SP
928: BNE loop
0018 26f1 [3/1] BNE *-13 ;abs = 000b
929:
930: LDAA 2,SP+ ;// restore old page value and release stack
001a a6b1 [3] LDAA 2,SP+
931: STAA PAGE_ADDR ;// store it into page register
001c 5a30 [2] STAA 48
932: LDX 4,SP+ ;// release stack and load return address
001e eeb3 [3] LDX 4,SP+
933: JMP 0,X ;// return
0020 0500 [3] JMP 0,X
934: }
935: #endif
936: }
937:
938: #else /* __HCS12X__ */
939:
940: /*
941: The HCS12X knows two different kind of addresses:
942: - Logical addresses. E.g.
943: MOVB #page(var),RPAGE
944: INC var
945:
946: - Global addresses E.g.
947: MOVB #page(var),GPAGE
948: GLDAA var
949: INCA
950: GSTAA var
951:
952: Global addresses are used with G-Load's and G-Store's, logical addresses are used for all the other instructions
953: and occasions. As HC12's or HCS12's do not have the G-Load and G-Store instructions,
954: global addresses are not used with these processor families.
955: They are only used with HCS12X chips (and maybe future ones deriving from a HCS12X).
956:
957: Logical and Global addresses can point to the same object, however the global and logical address of an object
958: are different for most objects (actually for all except the registers from 0 to 0x7FF).
959: Therefore the compiler needs to transform in between them.
960:
961: HCS12X Pointer types:
962:
963: The following are logical addresses:
964: - all 16 bit pointers
965: - "char* __near": always.
966: - "char *" in the small and banked memory model
967: - 24 bit dpage, epage, ppage or rpage pointers (*1) (note: the first HCS12X compilers may not support these pointer types)
968: - "char *__dpage": Note this type only exists for
969: orthogonality with the HC12 A4 chip which has a DPAGE reg.
970: It does not apply to the HCS12X.
971: - "char *__epage": 24 bit pointer using the EPAGE register
972: - "char *__ppage": 24 bit pointer using the PPAGE register.
973: As the PPAGE is also used for BANKED code,
974: using this pointer type is only legal from non banked code.
975: - "char *__rpage": 24 bit pointer using the RPAGE register
976:
977:
978: The following are global addresses:
979: "char*": in the large memory model (only HCS12X)
980: "char* __far": always for HCS12X.
981:
982: (*1): For the HC12 and HCS12 "char* __far" and "char*" in the large memory model are also logical.
983:
984: Some notes for the HC12/HCS12 programmers.
985:
986: The address of a far object for a HC12 and for a HCS12X is different, even if they are at the same place in the memory map.
987: For the HC12, a far address is using the logical addresses, for the HCS12X however, far addresses are using global addresses.
988: This does cause troubles for the unaware!
989:
990: HCS12X Logical Memory map
991:
992: Logical Addresses Used for shadowed at page register Global Address
993:
994: 0x000000 .. 0x0007FF Peripheral Registers Not Paged 0x000000
995: 0x??0800 .. 0x??0BFF Paged EEPROM EPAGE (@0x17) 0x100000+EPAGE*0x0400
996: 0x000C00 .. 0x000FFF Non Paged EEPROM 0xFF0800..0xFF0FFF Not Paged 0x13FC00
997: 0x??1000 .. 0x??1FFF Paged RAM RPAGE (@0x16) 0x000000+RPAGE*0x1000
998: 0x002000 .. 0x003FFF Non Paged RAM 0xFE1000..0xFF1FFF Not Paged 0x0FE000
999: 0x004000 .. 0x007FFF Non Paged FLASH 0xFC8000..0xFCBFFF Not Paged 0x7F4000
1000: 0x??8000 .. 0x00BFFF Paged FLASH PPAGE (@0x30) 0x400000+PPAGE*0x4000
1001: 0x00C000 .. 0x00FFFF Non Paged FLASH 0xFF8000..0xFFBFFF Not Paged 0x7FC000
1002:
1003: NA: Not Applicable
1004:
1005: HCS12X Global Memory map
1006:
1007: Global Addresses Used for Logical mapped at
1008:
1009: 0x000000 .. 0x0007FF Peripheral Registers 0x000000 .. 0x0007FF
1010: 0x000800 .. 0x000FFF DMA registers Not mapped
1011: 0x001000 .. 0x0FFFFF RAM 0x??1000 .. 0x??1FFF
1012: 0x0FE000 .. 0x0FFFFF RAM, Log non paged 0x002000 .. 0x003FFF
1013: 0x100000 .. 0x13FFFF EEPROM 0x??0800 .. 0x??0BFF
1014: 0x13FC00 .. 0x13FFFF EEPROM non paged 0x000C00 .. 0x000FFF
1015: 0x140000 .. 0x3FFFFF External Space Not mapped
1016: 0x400000 .. 0x7FFFFF FLASH 0x??8000 .. 0x??BFFF
1017: 0x7F4000 .. 0x7F7FFF FLASH, Log non paged 0x004000 .. 0x007FFF
1018: 0x7FC000 .. 0x7FFFFF FLASH, Log non paged 0x00C000 .. 0x00FFFF
1019:
1020:
1021: How to read this table:
1022: For logical addresses, the lower 16 bits of the address do determine in which area the address is,
1023: if this address is paged, then this entry also controls and which of the EPAGE, PPAGE or RPAGE
1024: page register is controlling the bits 16 to 23 of the address.
1025: For global addresses, the bits 16 to 23 have to be in the GPAGE register and the lower 16 bits
1026: have to be used with the special G load or store instructions (e.g. GLDAA).
1027: As example the logical address 0x123456 is invalid. Because its lower bits 0x3456 are in a
1028: non paged area, so the page 0x12 does not exist.
1029: The address 0xFE1020 however does exist. Do access it, the RPAGE has to contain 0xFE and the
1030: offset 0x1020 has to be used.
1031:
1032: ORG $7000
1033: MOVB #0xFE, 0x16 ; RPAGE
1034: LDAA 0x1020 ; reads at the logical address 0xFE1020
1035:
1036: Because the last two RAM pages are also accessible directly from 0x2000 to 0x3FFF, the
1037: following shorter code does read the same memory location:
1038:
1039: ORG $7000
1040: LDAA 0x2020 ; reads at the logical address 0x2020
1041: ; which maps to the same memory as 0xFE1020
1042:
1043: This memory location now also has a global address. For logical 0xFE1020 the global address is 0x0FE020.
1044: So the following code does once more access the same memory location:
1045:
1046: ORG $7000
1047: MOVB #0x0F, 0x10 ; GPAGE
1048: LDAA 0xE020 ; reads at the global address 0x0FE020
1049: ; which maps to the same memory as the logical addr. 0xFE1020
1050:
1051: Therefore every memory location for the HCS12X has up to 3 different addresses.
1052: Up to two logical and one global.
1053: Notes.
1054: - Not every address has ⌨️ 快捷键说明
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