simple_phy.c

FREESCALE 提供的 ZIGBEE协议

/**
 * Copyright (c) 2004, Freescale Semiconductor
 * Freescale Confidential Proprietary
 *
 * File name :  simple_phy.c
 * Project name: SMAC (Simple Media Access Controller)
 *
 * Department : Freescale Radio Products Division
 *
 * Description : This is the SMAC C source physical layer file for the HC(S)08
 * MCU and MC13192 transceiver.
 * The SMAC phy is the second lowest layer of C code.
 *
 * $Author: r01160 $
 * $Date: 2005/07/29 03:30:28 $
 * $Name:  $
 */

#include "MC13192_regs.h"
#include "MC13192_hw_config.h"
#include "pub_def.h"
#include "drivers.h"
#include "simple_phy.h"
#include "simple_mac.h"
#include "mcu_hw_config.h"


/* Globals */
extern tRxPacket *psDrvRxPacket;
extern UINT8 gu8RTxMode;

/* Version string to put in NVM. Note! size limits */
/* Normally it shoud be enough to change the version numbers. */
#define PHY_Version     "1.00"
#define PHY_Label       "SPHY "

#if defined (HCS08G) | defined (HCS08R)	| defined (_HCS12)
  #include <hidef.h>
#pragma MESSAGE DISABLE C3303  /* 
                                * Warning C3303: Implicit concatenation of 
                                * strings 
                                */
#pragma MESSAGE DISABLE C4200  /* 
                                * Warning C4200: Other segment than in previous 
                                * declaration
                                */
#pragma CONST_SEG BOOTLOADER_PHY_NV_DATA0
#endif

// DO NOT CHANGE OR REMOVE

// This string will be located in the NV RAM0 section.
// Note!! Check that item is location in the sequence as specified. 
const unsigned char SPHY_Version[47] = "PHY " PHY_Label " Ver " PHY_Version " Build: "__DATE__" "__TIME__;

#if defined (HCS08G) | defined (HCS08R) | defined (_HCS12)
#pragma CONST_SEG DEFAULT
#endif

/*
 * PDDataRequest : Transmit data packet
 *
 * Parameters : *psPacket - packet pointer
 *
 * Return : Status
 */
UINT8 PDDataRequest(tTxPacket *psPacket)
{
    if (gu8RTxMode == IDLE_MODE)
    { 
        RAMDrvWriteTx(psPacket);            /* Load the data into packet RAM */
        PLMESetTrxStateRequest(TX_MODE);    /* transmit it */

        /* Wait for the state to return to idle. (finish transmitting) */
        while (gu8RTxMode != IDLE_MODE)
        {
            MCU_LOW_POWER_WHILE();
        }
        return SUCCESS;
    }
    else
    {
        return RX_ON;
    }
}


/*
 * PDDataIndication : Receive data packet indication.
 *
 * Parameters : None
 *
 * Return : None
 */
void PDDataIndication()
{
    /* Read the Data only if it is a good packet. */
    if (psDrvRxPacket->u8Status == SUCCESS)
    {
        RAMDrvReadRx(psDrvRxPacket);         /* 
                                             * Read data from MC13192, 
                                             * check status 
                                             */
    }
    EnableInterrupts;       /* Allow system interrupts within the IRQ handler */
    MCPSDataIndication(psDrvRxPacket);
}


/*
 * PLMEHibernateRequest : Hibernate the MC13192 (very low current, no CLKO).
 *
 * Parameters : None
 *
 * Return : Status
 */
UINT8 PLMEHibernateRequest(void)
{
    UINT16 u16CurrentValue;
    
    gu8RTxMode = HIBERNATE_MODE;
    u16CurrentValue = SPIDrvRead(MODE2_ADDR);       /* 
                                                     * Read MC13192 Hiberate 
                                                     * register. 
                                                     */
    u16CurrentValue &= 0xFFFC;
    u16CurrentValue |= 0x0002;                      /* Hiberate enable */
    SPIDrvWrite(MODE2_ADDR, u16CurrentValue);       /* 
                                                     * Write back to MC13192 to 
                                                     * enable hibernate mode. 
                                                     */
    return SUCCESS;         /* Call back to MAC layer indicating success. */
}


/*
 * PLMEDozeRequest : Doze the MC13192 (Low current, CLKO <= 1MHz).
 *
 * Parameters : None
 *
 * Return : Status
 */
UINT8 PLMEDozeRequest(UINT32 u32Timeout)
{
    UINT16 u16CurrentValue;
    UINT32 u32CurrentTime;
    
    gu8RTxMode = DOZE_MODE;
    u16CurrentValue = SPIDrvRead(MODE2_ADDR);       /* 
                                                     * Read MC13192 Doze 
                                                     * register. 
                                                     */
    if (u32Timeout == 0)        /* ACOMA mode, with clkout */
    {
        u16CurrentValue = SPIDrvRead(IRQ_MASK);
        u16CurrentValue &= 0xFE0D;   /* Change the IRQ_Mask to set Acoma en,*/
        u16CurrentValue |= 0x0100;   /* doze irq disabled and tmr2 disabled*/
        SPIDrvWrite(IRQ_MASK, u16CurrentValue);      
        
        u16CurrentValue = SPIDrvRead(MODE2_ADDR);       /* 
                                                         * Read MC13192 Doze 
                                                         * register. 
                                                         */
        u16CurrentValue &= 0xFDFC;
        u16CurrentValue |= 0x0201;                      /* Doze (acoma) & CLKOUT enable */
        SPIDrvWrite(MODE2_ADDR, u16CurrentValue);       /* 
                                                         * Write back to MC13192 to 
                                                         * enable hibernate mode. 
                                                         */
    } else						 /* DOZE mode with timeout, no clkout */
    {
        u16CurrentValue = SPIDrvRead(IRQ_MASK);
        u16CurrentValue &= 0xFE0D;   /* Change the IRQ_Mask to set Acoma dis,*/
        u16CurrentValue |= 0x0012;   /* doze enabled and tmr2 enabled*/
        SPIDrvWrite(IRQ_MASK, u16CurrentValue);      
        
        u32CurrentTime = PLMEGetTimeRequest();
        u32Timeout += u32CurrentTime;
        SPIDrvWrite( T2_HI_ADDR, ((UINT16)(u32Timeout>>16)&0x00FF) ); 
        SPIDrvWrite( T2_LO_ADDR, ((UINT16)u32Timeout)&0xFFFF );  /* Enable the Timer 2 
                                                         * and save the timeout value
                                                         */
        u16CurrentValue = SPIDrvRead(MODE2_ADDR);
        u16CurrentValue &= 0xFDFC;						/* Disable CLKOinDozeand */
        u16CurrentValue |= 0x0001;                      /* enter in Doze mode */
        SPIDrvWrite(MODE2_ADDR, u16CurrentValue);      
    }
    return SUCCESS;         /* Call back to MAC layer indicating success. */
}


/*
 * PLMEWakeRequest : Wake the MC13192 from Hibernate or Doze.
 *
 * Parameters : None
 *
 * Return : Status
 */
UINT8 PLMEWakeRequest(void)
{
    UINT16 u16CurrentValue;
    
    MC13192Wake();                              /* Wake up the device */
    while (gu8RTxMode != IDLE_MODE_ATTN)
    {
        MCU_LOW_POWER_WHILE();                    /* Wait until ATTN */
    }
    u16CurrentValue = SPIDrvRead(MODE2_ADDR);       /* 
                                                     * Read MC13192 
                                                     * Hibernate/Doze register. 
                                                     */
    u16CurrentValue &= 0xFFFC;                  /* Hiberate and Doze disable */
    SPIDrvWrite(MODE2_ADDR, u16CurrentValue);       /* 
                                                     * Write back to MC13192 to 
                                                     * disable hibernate and doze 
                                                     * mode. 
                                                     */
    SPIDrvWrite(T2_HI_ADDR, 0x0000);                /* Disable Timer2
                                                     * To avoid a T2 int because
                                                     * of doze w/timeout
                                                     */
    gu8RTxMode = IDLE_MODE;
    return SUCCESS;
}


/*
 * PLMESetChannelRequest : Set the MC13192 operating channel.
 *
 * Parameters : u8Channel - Channel number
 *
 * Return : Status
 */
UINT8 PLMESetChannelRequest(UINT8 u8Channel)
{
    switch (u8Channel)
    {
    case 0x00:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F95);
        SPIDrvWrite(LO1_NUM_ADDR,0x5000);
    break;
    case 0x01:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F95);
        SPIDrvWrite(LO1_NUM_ADDR,0xA000); 
    break;
    case 0x02:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F95);
        SPIDrvWrite(LO1_NUM_ADDR,0xF000); 
    break;
    case 0x03:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F96);
        SPIDrvWrite(LO1_NUM_ADDR,0x4000); 
    break;
    case 0x04:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F96);
        SPIDrvWrite(LO1_NUM_ADDR,0x9000); 
    break;
    case 0x05:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F96);
        SPIDrvWrite(LO1_NUM_ADDR,0xE000); 
    break;
    case 0x06:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F97);
        SPIDrvWrite(LO1_NUM_ADDR,0x3000); 
    break;
    case 0x07:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F97);
        SPIDrvWrite(LO1_NUM_ADDR,0x8000); 
    break;
    case 0x08:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F97);
        SPIDrvWrite(LO1_NUM_ADDR,0xD000); 
    break;
    case 0x09:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F98);
        SPIDrvWrite(LO1_NUM_ADDR,0x2000); 
    break;
    case 0x0A:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F98);
        SPIDrvWrite(LO1_NUM_ADDR,0x7000); 
    break;
    case 0x0B:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F98);
        SPIDrvWrite(LO1_NUM_ADDR,0xC000); 
    break;
    case 0x0C:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F99);
        SPIDrvWrite(LO1_NUM_ADDR,0x1000); 
    break;
    case 0x0D:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F99);
        SPIDrvWrite(LO1_NUM_ADDR,0x6000); 
    break;
    case 0x0E:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F99);
        SPIDrvWrite(LO1_NUM_ADDR,0xB000); 
    break;
    case 0x0F:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F9A);
        SPIDrvWrite(LO1_NUM_ADDR,0x0000); 
    break;
    default:
        SPIDrvWrite(LO1_IDIV_ADDR,0x0F97);
        SPIDrvWrite(LO1_NUM_ADDR,0xD000); 
        return ERROR;
    }
    return SUCCESS;
}


/*
 * PLMESetTrxStateRequest : Set the MC13192 transceive operation.
 *
 * Parameters : Operational mode
 *
 * Return : Status
 */
UINT8 PLMESetTrxStateRequest(UINT8 u8ReqMode)
{
    UINT16 u16Reg;
    
    RTXENDeAssert(); 
    u16Reg = SPIDrvRead(MODE_ADDR);
    u16Reg &= 0xFFF8;                           /* Clear mode. */
    switch (u8ReqMode)
    {
        case IDLE_MODE:                         /* Write Idle */
        #if defined (LNA)
            MC13192_LNA_CTRL = LNA_OFF;
        #endif
        #if defined (PA)
            MC13192_PA_CTRL = PA_OFF;
        #endif
        u16Reg |= IDLE_MODE;
        gu8RTxMode = IDLE_MODE;
        SPIDrvWrite(MODE_ADDR, u16Reg);
        break;

        case RX_MODE:                           /* Write RX */
        #if defined (LNA)
            MC13192_LNA_CTRL = LNA_ON;
        #endif
        #if defined (PA)
            MC13192_PA_CTRL = PA_OFF;
        #endif
        #if defined (ANTENNA_SWITCH)
            MC13192_ANT_CTRL2 = ANT_CTRL_ON;    /* Turn on the RX antenna */
            MC13192_ANT_CTRL = ANT_CTRL_OFF;    /* Turn off the TX antenna */
        #endif
        gu8RTxMode = RX_MODE;
        u16Reg |= RX_MODE;
        SPIDrvWrite(MODE_ADDR, u16Reg);
        RTXENAssert(); 
        break;
        
        case RX_MODE_WTO:           /* Write RX, but set gu8RTxMode to timeout */
        #if defined (LNA)
            MC13192_LNA_CTRL = LNA_ON;
        #endif
        #if defined (PA)
            MC13192_PA_CTRL = PA_OFF;
        #endif
        #if defined (ANTENNA_SWITCH)
            MC13192_ANT_CTRL2 = ANT_CTRL_ON;    /* Turn on the RX antenna */
            MC13192_ANT_CTRL = ANT_CTRL_OFF;    /* Turn off the TX antenna */
        #endif
        gu8RTxMode = RX_MODE_WTO;
        u16Reg |= RX_MODE;
        SPIDrvWrite(MODE_ADDR, u16Reg);
        RTXENAssert();
        break;
        
        case TX_MODE:               /* Write Tx. Note: force LO lock not used */
        #if defined (PA)
            MC13192_PA_CTRL = PA_ON;
        #endif
        #if defined (LNA)
            MC13192_LNA_CTRL = LNA_OFF;
        #endif
        #if defined (ANTENNA_SWITCH)
            MC13192_ANT_CTRL2 = ANT_CTRL_OFF;   /* Turn off the RX antenna */
            MC13192_ANT_CTRL = ANT_CTRL_ON;     /* Turn on the TX antenna */
        #endif
        u16Reg |= TX_MODE;
        gu8RTxMode = TX_MODE;
        SPIDrvWrite(MODE_ADDR, u16Reg);
        RTXENAssert();
        break;
        
        case PULSE_TX_MODE: /* Write Tx. Note: force LO lock not used */

		  #if defined (PA)
  	         MC13192_PA_CTRL = PA_ON;
		  #endif