nand.h

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/*
*Garfield EMI Nand Flash controller registers added
*Xiaoj 2004.2.28
*
*/
/*
 * Standard NAND flash commands							
 */
#define NAND_CMD_READ0		0x80000000                                     //highesn bit means enable in GIII controller
#define NAND_CMD_READ1		1
#define NAND_CMD_PAGEPROG	0x10
#define NAND_CMD_READOOB		0x50
#define NAND_CMD_ERASE1		0x80000060
#define NAND_CMD_STATUS		0x80000070
#define NAND_CMD_SEQIN		0x80000080
#define NAND_CMD_READID		0x90
#define NAND_CMD_ERASE2		0xd0
#define NAND_CMD_RESET		0x800000ff


#define  GFD_NAND_REGBASE			 0x11000100 			 	 //NAND FLASH register base;
#define  GFD_DMA_REGBASE			 0x11001000 

#define	 GFD_NAND_ADDR				( GFD_NAND_REGBASE+0X00  )	 //adress of Nand Flash adress register
#define	 GFD_NAND_COM				( GFD_NAND_REGBASE+0X04  )	 //adress of Nand Flash control register
#define	 GFD_NAND_STATUS			( GFD_NAND_REGBASE+0X0c  )	 //adress of Nand Flash status register
#define	 GFD_NAND_ERRORADDR1		( GFD_NAND_REGBASE+0X10  )	 //adress of Nand Flash error register I
#define	 GFD_NAND_ERRORADDR2		(GFD_NAND_REGBASE+0X14  )	 //adress of Nand Flash error register II                                             
#define	 GFD_NAND_CONF				( GFD_NAND_REGBASE+0X18  )	 //adress of Nand Flash config register
#define    GFD_NAND_INTR			(GFD_NAND_REGBASE+0X1c  )	 //Int clear
#define    GFD_NAND_FINECC			(GFD_NAND_REGBASE+0X20  ) 	 //ECC complish
#define    GFD_NAND_IDLE			(GFD_NAND_REGBASE+0X24  ) 	 //Compish register
#define    GFD_NAND_DATA			(GFD_NAND_REGBASE+0X100  ) 	 //0x11000200



#define 	DMACbase					0x11000000
#define 	DMACIntStatus				(DMACbase+0x1020) 			//Read
#define 	DMACIntTCStatus				(DMACbase+0x1050) 			//Read
#define 	DMACIntTCClear				(DMACbase+0x1060) 			//Write
#define 	DMACRawIntTCStatus			(DMACbase+0x1070) 			//Read
#define 	DMACIntErrorStatus			(DMACbase+0x1080) 			//Read
#define 	DMACIntErrClr				(DMACbase+0x1090) 			//Write
#define 	DMACRawIntErrorStatus		(DMACbase+0x10a0) 			//Read
#define 	DMACEnbldChns				(DMACbase+0x10B0) 			//Read;  Indicate which channel can be used;
#define   ADDRESS_CONFIGURATION 		(DMACbase+0x10C0)
   
#define 	DMACC0SrcAddr				(DMACbase+0x1000)			//DMA channel 0 registers;
#define 	DMACC0DestAddr				(DMACbase+0x1004)
#define 	DMACC0Control				(DMACbase+0x100c)
#define 	DMACC0Configuration			(DMACbase+0x1010)

#define 	DMACC1SrcAddr				(DMACbase+0x1100)			//DMA channel 1 registers;
#define 	DMACC1DestAddr				(DMACbase+0x1104)
#define 	DMACC1Control				(DMACbase+0x110c)
#define 	DMACC1Configuration			(DMACbase+0x1110)

#define 	DMACC2SrcAddr				(DMACbase+0x1200)			//DMA channel 2 registers;   R/W
#define 	DMACC2DestAddr				(DMACbase+0x1204)
#define 	DMACC2Control				(DMACbase+0x120c)
#define 	DMACC2Configuration			(DMACbase+0x1210)