📄 sd_defs.h
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/*************************************************************************/
/* */
/* Copyright (c) 2000 Accelerated Technology, Inc. */
/* */
/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
/* subject matter of this material. All manufacturing, reproduction, */
/* use, and sales rights pertaining to this subject matter are governed */
/* by the license agreement. The recipient of this software implicitly */
/* accepts the terms of the license. */
/* */
/*************************************************************************/
/*************************************************************************/
/* */
/* FILE NAME VERSION */
/* */
/* sd_defs.h PLUS/KS32C41000 1.11.1 */
/* */
/* COMPONENT */
/* */
/* SD - Serial Driver */
/* */
/* DESCRIPTION */
/* */
/* This file contains constant definitions and function macros */
/* for the Serial Driver module. */
/* */
/* DATA STRUCTURES */
/* */
/* SD_PORT : Structure to keep all needed info. about a port. */
/* */
/* DEPENDENCIES */
/* */
/* none */
/* */
/*************************************************************************/
#ifndef SD_DEFS_H
#define SD_DEFS_H
/**************** User configurable section *****************************/
/* The default system clock on the KS32C41000 Evaluation board is 40MHz */
#define SYSTEM_CLOCK 45200000
/**************** End configurable section *************************/
/* Defines for reading and writing the KS32C41000 Interrupt Control and
Mask registers. */
#define INTCON 0x1E00000 /* Sets Mode and IRQ/FIQ Enable/Disable */
#define INTPND 0x1E00004 /* 1= IRQ unmasked and active */
#define INTMOD 0x1E00008 /* 1= FIQ ---- 0= IRQ */
#define INTMSK 0x1E0000c /* 1= INT Masked -- 0= INT Enabled */
/* NOTE: Samsung Documentation states that these two registers can be
** accessed only once from an ISR!
**************************************************************************/
#define I_ISPC 0x1E00024 /* Write 1 to Active IRQ to reset it */
#define F_ISPC 0x1E0003C /* Write 1 to Active FIQ to reset it */
/* Defines for fields and bits of interrupt control and mask registers. */
#define SD_IMR_MASTER_MASK (1 << 26) /* Global IRQ Enable */
#define SD_IMR_UART1_TX_MASK (1 << 3) /* UART 1 Tx IRQ is Bit 3 */
#define SD_IMR_UART2_TX_MASK (1 << 2) /* UART 2 Tx IRQ is Bit 2 */
#define SD_IMR_UART1_RX_MASK (1 << 7) /* UART 1 Rx IRQ is Bit 7 */
#define SD_IMR_UART2_RX_MASK (1 << 6) /* UART 2 Rx IRQ is Bit 6 */
/* Defines for specifying which UART to use. */
#define SD_UART1 1
#define SD_UART2 2
#define SD_MAX_UARTS 2
/* Defines for reading and writing the UART control registers */
#define SD_UART1_BASE_OFFSET 0x01D00000
#define SD_UART2_BASE_OFFSET 0x01d04000
/* UART register offsets from the UART base. Data written in low byte. */
#define SD_ULCON_OFFSET 0x00 /* UART 1/2 Line Control Reg */
#define SD_UCON_OFFSET 0x04 /* UART 1/2 Channel Control Reg */
#define SD_USTAT_OFFSET 0x10 /* UART 1/2 Channel Status Reg */
#define SD_UFCON_OFFSET 0x08 /* UART FIFO Control Reg */
#define SD_UFSTAT_OFFSET 0x18 /* UART FIFO Status Reg */
/* The function of these registers depend upon the FIFO Mode selected
** (or not) See Pages 10-13 & 10-14 in KS32C41000 User's Manual. */
#define SD_UTXH_OFFSET 0x20 /* Big Endian - Data in Upper byte */
#define SD_URXH_OFFSET 0x24 /* Big Endian - Data in Upper byte */
/** NOTE: 16 Bit Register
** UART Baud Rade Divison (UBRDIVx) Register
**
** Baud Rate Value = ( (int)(mclk/16./baud + 0.5)-1 );
************************************************************************/
#define SD_UBRDIV_OFFSET 0x28 /* UART Baud Rate Divisor register */
/******* Defines for fields and bits of UART control registers *********/
/* These use generic type names, leaving off the register nameo, because
they are used by generic sections of code which will not require
changes for other UARTS. Only the bits these correspond to should
change. */
/* For the Samsung 41000 these functions are controlled via the UART
** Line Control (ULCONx) Registers *************************************/
#define SD_ULCON_RESERVED 0x80
#define SD_MODE_NORMAL 0x40 /* 0=Normal -- 1=IR Mode */
#define SD_PARITY_NONE 0x00 /* 0=NONE -- 1=Enabled */
#define SD_PARITY_EVEN 0x28 /* 0=NONE -- 1=Enabled */
#define SD_PARITY_ODD 0x20 /* 00=Odd ---- 01=Even */
/* 10=Forced - Checked as 1 */
/* 11=Forced - Checked as 0 */
#define SD_STOP_BITS_1 0x00 /* Bit 2=0 1 Stop Bit */
#define SD_STOP_BITS_2 0x04 /* Bit 2=1 2 Stop Bits */
#define SD_DATA_BITS_5 0x00
#define SD_DATA_BITS_6 0x01
#define SD_DATA_BITS_7 0x02
#define SD_DATA_BITS_8 0x03
/* These use specific type names, putting the register name
in the macro, because these macros are used by port specific
sections of code and will most likely have different names
on other UARTS. */
/**************** UART Control Register (UCONx) Bits ********************
** NOTE: T/O avialable ONLY for UART 0 ! ********************/
#define SD_UCON0_TIMEOUT 0x80 /* 1=Enable FIFO Empty IRQ */
#define SD_UCON_RX_IRQ 0x40 /* 1=Enable Rx IRQ */
#define SD_UCON_LOOPBACK 0x20 /* 1=Enable Loopback Mode */
#define SD_UCON_TX_BREAK 0x10 /* 1=Send Break signal */
#define SD_UCON_TX_MODE_MASK 0x0C /* 00=Disabled */
#define SD_UCON_TX_MODE_IRQ 0x04 /* 01=IRQ or Polled Mode */
/* 10=BDMA0 (Buffered DMA0) */
/* 11=BDMA0 (Buffered DMA1) */
#define SD_UCON_RX_MODE_MASK 0x03 /* 00=Disabled */
#define SD_UCON_RX_MODE_IRQ 0x01 /* 01=IRQ or Polled Mode */
/* 10=BDMA0 (Buffered DMA0) */
/* 11=BDMA0 (Buffered DMA1) */
#define SD_UCON_DISABLE 0x00 /* 00=Disable All Functions */
/***************** UART Status Register (USTATx) Bits *******************/
#define SD_USTAT_TSH_EMPTY 0x04 /* 1=Tx Holding & Shift Reg **
** Both Empty */
#define SD_USTAT_TX_EMPTY 0x02 /* 1=Tx FIFO or Buffer NOT **
** Empty */
#define SD_USTAT_RXRDY 0x01 /* 1=Rx Data Ready */
#define SD_USTAT0_RX_T_O 0x01 /* 1=Rx T/O - UART 0 Only */
#define SD_USTAT_BREAK_DET 0x08 /* 1=Break received */
#define SD_USTAT_FRAME_ERR 0x04 /* 1=Rx Frame Error */
#define SD_USTAT_PARITY_ERR 0x02 /* 1=Rx pARITY Error */
#define SD_USTAT_OVERRUN_ERR 0x01 /* 1=Rx Overrun Error */
/*************** UART FIFO Control Register (UFCON0) Bits ***************/
#define SD_UFCON_TX_FIFO_TRIG 0xC0 /* 00=IRQ on Tx FIFO Empty */
/* 01=IRQ when Tx FIFO = 4 */
/* 10=IRQ when Tx FIFO = 8 */
/* 01=IRQ when Tx FIFO = 12 */
#define SD_UFCON_RX_FIFO_TRIG 0x30 /* 00=IRQ when Rx FIFO = 4 */
/* 01=IRQ when Rx FIFO = 8 */
/* 10=IRQ when Rx FIFO = 12 */
/* 01=IRQ when Rx FIFO = 16 */
#define SD_UFCON_RESERVED 0x08 /* Bit 3 is Reserved */
#define SD_UFCON_TX_FIFO_RESET 0x04 /* 1=Tx FIFO Reset */
#define SD_UFCON_RX_FIFO_RESET 0x02 /* 1=Rx FIFO Reset */
#define SD_UFCON_FIFO_ENABLE 0x01 /* 1=FIFO (Tx & Rx) Enable */
#define SD_UFCON_DISABLE 0x00 /* 00=Disable All Functions */
/** NOTE: 16 Bit Register!
** UART FIFO Status Register (UFSTATx) Bits */
#define SD_UFSTAT_RESERVED 0xFC00 /* Bits 15-->10 Reserved */
#define SD_UFSTAT_TX_FIFO_FULL 0x0200 /* Bit 9 =1 =Tx FIFO Full */
#define SD_UFSTAT_RX_FIFO_FULL 0x0100 /* Bit 8 =1 =Tx FIFO Full */
#define SD_UFSTAT_TX_FIFO_CNT 0x00F0 /* Number bytes in Tx FIFO */
#define SD_UFSTAT_RX_FIFO_CNT 0x000F /* Number bytes in Rx FIFO */
/* Define data structures for management of a serial port. */
typedef volatile struct SD_INIT_STRUCT
{
UNSIGNED data_mode;
UNSIGNED base_address;
/* The following elements should be generic across platforms. */
NU_SEMAPHORE *sd_semaphore;
UNSIGNED com_port;
UNSIGNED data_bits;
UNSIGNED stop_bits;
UNSIGNED parity;
UNSIGNED baud_rate;
UNSIGNED vector;
UNSIGNED driver_options;
UNSIGNED sd_buffer_size;
UNSIGNED parity_errors;
UNSIGNED frame_errors;
UNSIGNED overrun_errors;
UNSIGNED busy_errors;
UNSIGNED general_errors;
CHAR *rx_buffer;
volatile INT rx_buffer_read;
volatile INT rx_buffer_write;
volatile INT rx_buffer_status;
/* All of the following elements are required by PPP, do not modify. */
UNSIGNED communication_mode;
CHAR *tx_buffer;
volatile INT tx_buffer_read;
volatile INT tx_buffer_write;
volatile INT tx_buffer_status;
} SD_PORT;
/* Defines to be used by application */
#define MODE_NORMAL SD_MODE_NORMAL
#define MODE_AUTO_ECHO SD_MODE_AUTO_ECHO
#define MODE_LOCAL_LOOP SD_MODE_LOCAL_LOOP
#define MODE_REMOTE_LOOP SD_MODE_REMOTE_LOOP
#define STOP_BITS_1 SD_STOP_BITS_1
#define STOP_BITS_2 SD_STOP_BITS_2
#define UART1 SD_UART1
#define UART2 SD_UART2
/* Defines to determine communication mode */
#define SERIAL_MODE 0
#define MDM_NETWORK_COMMUNICATION 1
#define MDM_TERMINAL_COMMUNICATION 2
/************************************************************
** Note: everything below should be genric. */
#define NU_SERIAL_PORT SD_PORT
#define PARITY_NONE SD_PARITY_NONE
#define PARITY_EVEN SD_PARITY_EVEN
#define PARITY_ODD SD_PARITY_ODD
#define DATA_BITS_6 SD_DATA_BITS_6
#define DATA_BITS_7 SD_DATA_BITS_7
#define DATA_BITS_8 SD_DATA_BITS_8
#define NU_SD_Put_Char SDC_Put_Char
#define NU_SD_Get_Char SDC_Get_Char
#define NU_SD_Put_String SDC_Put_String
#define NU_SD_Init_Port SDC_Init_Port
#define NU_SD_Data_Ready SDC_Data_Ready
#define NU_UART_SUCCESS 0
#define NU_INVALID_PARITY -1
#define NU_INVALID_DATA_BITS -2
#define NU_INVALID_STOP_BITS -3
#define NU_INVALID_BAUD -4
#define NU_INVALID_COM_PORT -5
#define NU_INVALID_DATA_MODE -6
#define NU_UART_LIST_FULL -7
#define NU_BUFFER_FULL 1
#define NU_BUFFER_DATA 2
#define NU_BUFFER_EMPTY 3
/* Deifine I/O macros. */
/* 8 bit access */
#define SD_OUTBYTE(reg, data) ( (*( (volatile CHAR *) (reg) ) ) = (data) )
#define SD_INBYTE(reg) ( *( (volatile CHAR *) (reg) ) )
/* 16 bit access */
#define SD_OUTWORD(reg, data) ( (*( (volatile unsigned short *) (reg) ) ) = (data) )
#define SD_INWORD(reg) ( *( (volatile unsigned short *) (reg) ) )
/* 32 bit access */
#define SD_OUTDWORD(reg, data) ( (*( (volatile UNSIGNED *) (reg) ) ) = (data) )
#define SD_INDWORD(reg) ( *( (volatile UNSIGNED *) (reg) ) )
/* Macro used for converting URT to SD_PORT. This is for PPP serial driver
backwards compatability. */
#define URT_LAYER SD_PORT
#define URT_TX_BUFFER_SIZE uart->sd_buffer_size
#define URT_Get_Char SDC_Get_Char
#define URT_Put_Char SDC_Put_Char
#define URT_Reset SDC_Reset
#define URT_Change_Communication_Mode SDC_Change_Communication_Mode
#define URT_Carrier SDC_Carrier
#endif /* ifndef SD_DEFS_H */
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