int.s

基于nucleus操作系统的GPRS无线数据传输终端全套源文件。包括支持ARM7的BSP,操作系统

;/*************************************************************************/
;/*                                                                       */
;/* FILE NAME                                            VERSION          */
;/*                                                                       */
;/*      int.s                                       KS32C41100 1.0       */
;/*                                                                       */
;/* COMPONENT                                                             */
;/*                                                                       */
;/*      IN - Initialization                                              */
;/*                                                                       */
;/* DESCRIPTION                                                           */
;/*                                                                       */
;/*      This file contains the target processor dependent initialization */
;/*      routines and data.                                               */
;/*                                                                       */
;/* AUTHOR                                                                */
;/*      Meng.chen                                                        */
;/*                                                                       */
;/* DATA STRUCTURES                                                       */
;/*                                                                       */
;/*                              									      */
;/*                                                                       */
;/* FUNCTIONS                                                             */
;/*                                                                       */
;/*      Board_Init                     	 Target initialization        */
;/*                                                                       */
;/* DEPENDENCIES                                                          */
;/*                                                                       */
;/*                                								          */
;/*                                                                       */
;/* HISTORY                                                               */
;/*                                                                       */
;/*         NAME            DATE                    REMARKS               */
;/*                                                                       */
;/*		   M. Chen		  2002-07-12	  Created initial version 1.0     */
;/*                                                                       */
;/*************************************************************************/

;
;/* H/W definitions */
;
;System Controller
SYSCFG		EQU		0x01c00000		; System Configuration
WTCON		EQU		0x01d30000		; Watchdog timer
PLLCON		EQU		0x01d80000		; PLL Control
CLKCON		EQU		0x01d80004		; Clock Controller

;Memory Controller
BWSCON		EQU		0X01c80000

; Interrupt controller
INTCON		EQU		0x01e00000		; Interrupt Control
INTPND		EQU		0x01e00004		; Interrupt Request Status
INTMOD		EQU		0x01e00008		; Interrupt Mode Control
INTMSK		EQU		0x01e0000c		; Interrupt Mask Control
I_ISPR		EQU		0x01e00020		; IRQ Interrupt Pending Status
I_ISPC		EQU		0x01e00024		; IRQ Interrupt Pending Clear
F_ISPC		EQU		0x01e0003C		; FIQ Interrupt Pending Clear

; System tick timer registers and values
TCFG0		EQU		0x01d50000		; Timer Configuration
TCFG1		EQU		0x01d50004		; Timer Configuration
TCON		EQU		0x01d50008		; Timer Control
TCNTB0		EQU		0x01d5000c		; Timer Count Buffer 0


TCFG0_INIT_VAL	EQU		0x000000f9	; pre = 249+1
TCFG1_INIT_VAL	EQU		0x00000002	; mux = 1/8
TCNTB_5MS		EQU		100			; 40M/2000 = 20K(0.05ms)
TCNTB_10MS		EQU		200
TCNTB_20MS		EQU		400

TIMER0_LOAD		EQU		0x00000002	; Update Count Buffer
TIMER0_START	EQU		0x00000009	; Interval Mode, Start!		

TIMER0_MASK_BIT	EQU		0x00002000	; bit 13 in INTMSK
GLOBAL_MASK_BIT	EQU		0x04000000

	
	AREA |C$CODE|, CODE, READONLY
	
;
;Memory Controller Init Data
;	
SMR_DATA
	DCD		0x11110110		;BWSCON
	DCD		0x00000600		;GCS0
	DCD		0x00007ffc		;GCS1
	DCD		0x00007ffc		;GCS2
	DCD		0x00007ffc		;GCS3
	DCD		0x00007ffc		;GCS4
	DCD		0x00007ffc		;GCS5
	DCD		0x00018000		;GCS6
	DCD		0x00018000		;GCS7
	DCD		0x00860459		;REFRESH
	DCD		0x00000010		;BANKSIZE
	DCD		0x00000020		;MRSR
	DCD		0x00000020		;MRSR
	
	ALIGN

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		
;
;VOID Board_Init(VOID)
;
	EXPORT	Board_Init
Board_Init
; Initialize system configuration and memory map
	LDR		r0,=SYSCFG
	LDR		r1,=0x0e					;WB enable,Cache 8KB,stall disable
	STR		r1,[r0]

; Disable watch-dog timer
	LDR		r0,=WTCON
	LDR		r1,=0x0         
	str		r1,[r0]

; System clock control -- Fin=10MHz,Fout=40MHz,P/M/S=6/0x78/2
	ldr		r0,=PLLCON
; In order to use iis, Fout=45200000	
	;ldr		r1,=((0x6<<4)+(0x78<<12)+0x2)
	ldr		r1,=((0x17<<4)+(0x69<<12)+0x0)
	str		r1,[r0]

	ldr		r0,=CLKCON       
	ldr		r1,=0x7ff8					;All function-block CLKs enable
	str		r1,[r0]

;
; /* Initialize memory controller registers */
;
	ldr		r0,=SMR_DATA
	ldmia	r0,{r1-r13}
	ldr		r0,=BWSCON
	stmia	r0,{r1-r13}

; /*
;   If the board has an interrupt controller,
;   turn off the interrupt here if possible.
;  */
	LDR		r1, =INTCON
	LDR		r0, =0x7			; Non-vectored mode/IRQ & FIQ all disable
	STR		r0, [r1]
	
	LDR		r1, =INTMSK
	LDR		r0, =0x07ffffff		; all masked
	STR		r0, [r1]

	LDR		r1, =INTMOD
	LDR		r0, =0x0			; all -> IRQ
	STR		r0, [r1]

	LDR		r1, =I_ISPC
	LDR		r0, =0x3ffffff		; all IRQ pending bits clear
	STR		r0, [r1]

	LDR		r1, =F_ISPC
	LDR		r0, =0x3ffffff		; all FIQ pending bits clear
	STR		r0, [r1]

;
; use PWM timer 0 as system clock tick timer
; MCLK = 40MHz
; Timer0 input = 40MHz / 2000 = 20KHz
;
	LDR		a1,=TCFG0			;prescaler = 249+1
	LDR		a2,=TCFG0_INIT_VAL
	STR		a2,[a1,#0]
	
	LDR		a1,=TCFG1			;mux = 1/8 
	LDR		a2,=TCFG1_INIT_VAL
	STR		a2,[a1,#0]

	LDR		a1,=TCNTB0			;tick = 10ms
	LDR		a2,=TCNTB_10MS
	STR		a2,[a1,#0]

	LDR		a1,=TCON
	LDR		a2,=TIMER0_LOAD
	STR		a2,[a1,#0]
	LDR		a2,=TIMER0_START	;start timer0, but interrupt disabled
	STR		a2,[a1,#0]

	LDR		a1,=INTMSK
	LDR		a2,[a1,#0]
	MOV		a3,#TIMER0_MASK_BIT
	BIC		a2,a2,a3
	MOV		a3,#GLOBAL_MASK_BIT
	BIC		a2,a2,a3
	STR		a2,[a1,#0]

	LDR		a1,=INTCON
	LDR		a2,[a1,#0]
	MOV		a3,#2				;enable IRQ bit
	BIC		a2,a2,a3
	STR		a2,[a1,#0]

	MOV		pc, r14				;return

	END