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;
OLD_FIQ_VECT
DCD &00000000
;
OLD_FIQ_ADDR
DCD &00000000
ALIGN
;
;
;/*************************************************************************/
;/* */
;/* FUNCTION */
;/* */
;/* INT_Initialize */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function sets up the global system stack variable and */
;/* transfers control to the target independent initialization */
;/* function INC_Initialize. Responsibilities of this function */
;/* include the following: */
;/* */
;/* - Setup necessary processor/system control registers */
;/* - Initialize the vector table */
;/* - Setup the system stack pointers */
;/* - Setup the timer interrupt */
;/* - Calculate the timer HISR stack and priority */
;/* - Calculate the first available memory address */
;/* - Transfer control to INC_Initialize to initialize all of */
;/* the system components. */
;/* */
;/* AUTHOR */
;/* */
;/* Gai, Feng, Watertek, Inc. */
;/* */
;/* CALLED BY */
;/* */
;/* Nothing. This function is the ENTRY point for Nucleus PLUS. */
;/* */
;/* CALLS */
;/* */
;/* INC_Initialize Common initialization */
;/* */
;/* INPUTS */
;/* */
;/* None */
;/* */
;/* OUTPUTS */
;/* */
;/* None */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* */
;/* F. Gai 2000-04-03 Created initial version 1.0 */
;/* */
;/*************************************************************************/
;VOID INT_Initialize(void)
;{
EXPORT INT_Initialize
INT_Initialize
;
; /* Insure that the processor is in supervisor mode. */
;
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
ORR a1,a1,#LOCKOUT ; Insure IRQ/FIQ interrupts are locked out
MSR CPSR_cxsf,a1 ; Setup the new CPSR
BL Board_Init ; init On_board hardware
;
; /* setup vector table at EXPHDL_TBLBASE */
;
LDR a1,=INT_Table
LDR a2,=EXPHDL_TBLBASE
LDMIA a1!,{v1-v4}
STMIA a2!,{v1-v4}
LDMIA a1!,{v1-v4}
STMIA a2!,{v1-v4}
;
; /* Initialize memory values. Any intial values for any intialized
; variables are copied from ROM to RAM. In addition, this code
; clears the un-initialized global and static C data areas.
; Please see ARM User Guide Chapter 13, Writing Code for ROM
; for more details. */
;
;LDR a1,[pc, #ROM_Data_Start_Ptr-.-8]; Get the start of the
LDR a1,=ROM_Data_Start_Ptr
LDR a1,[a1,#0]
;LDR a2,[pc, #RAM_Start_Ptr-.-8] ; Get the start of the
LDR a2,=RAM_Start_Ptr
LDR a2,[a2,#0]
;LDR a4,[pc, #BSS_Start_Ptr-.-8] ; Pickup the start of
LDR a4,=BSS_Start_Ptr
LDR a4,[a4,#0]
CMP a1,a2 ; Check for any initial
; variable values
BEQ INT_BSS_Clear ; If none, zero memory
;
INT_ROM_Vars_Copy
CMP a2,a4 ; Check to set flags
LDRCC a3, [a1], #4 ; Get value from ROM
STRCC a3, [a2], #4 ; Put value in RAM
BCC INT_ROM_Vars_Copy ; Continue
;
INT_BSS_Clear
;LDR a2,[pc, #BSS_End_Ptr-.-8] ; Pickup the end of the BSS area
LDR a2,=BSS_End_Ptr
LDR a2,[a2,#0]
MOV a3,#0 ; Clear value in a3
;
INT_BSS_Clear_Loop
CMP a4,a2 ; Are the start and end equal?
STRCC a3,[a4],#4 ; Clear a word
BCC INT_BSS_Clear_Loop ; If so, continue with BSS clear
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; /* Initialize the system stack pointers. This is done after the BSS is
; clear because the TCD_System_Stack pointer is a BSS variable! It is
; assumed that available memory starts immediately after the end of the
; BSS section. */
;
;LDR a1,[pc, #BSS_End_Ptr-.-8] ; Pickup the ending address of BSS
LDR a1,=BSS_End_Ptr
LDR a1,[a1,#0]
MOV a2,#SYSTEM_SIZE ; Pickup system stack size
SUB a2,a2,#4 ; Subtract one word for first addr
ADD a3,a1,a2 ; Build start of system stack area
BIC a3,a3,#3 ; Insure word aligment of stack
MOV v7,a1 ; Setup initial stack limit
;LDR a4,[pc, #System_Limit-.-8] ; Pickup sys stack limit addr
LDR a4,=System_Limit
LDR a4,[a4,#0]
STR v7,[a4, #0] ; Save stack limit
MOV sp,a3 ; Setup initial stack pointer
;LDR a4,[pc, #System_Stack-.-8] ; Pickup system stack address
LDR a4,=System_Stack
LDR a4,[a4,#0]
STR sp,[a4, #0] ; Save stack pointer
MOV a2,#IRQ_STACK_SIZE ; Pickup IRQ stack size in bytes
ADD a3,a3,a2 ; Allocate IRQ stack area
BIC a3,a3,#3 ; Insure word alignment
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#IRQ_MODE ; Set the IRQ mode bits
MSR CPSR_cxsf,a1 ; Move to IRQ mode
MOV sp,a3 ; Setup IRQ stack pointer
MOV a2,#FIQ_STACK_SIZE ; Pickup FIQ stack size in bytes
ADD a3,a3,a2 ; Allocate FIQ stack area
BIC a3,a3,#3 ; Insure word alignment
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#FIQ_MODE ; Set the FIQ mode bits
MSR CPSR_cxsf,a1 ; Move to the FIQ mode
MOV sp,a3 ; Setup FIQ stack pointer
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear mode bits
ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
MSR CPSR_cxsf,a1 ; All interrupt stacks are setup,
; return to supervisor mode
;
; /* Define the global data structures that need to be initialized by this
; routine. These structures are used to define the system timer
; management HISR. */
; TMD_HISR_Stack_Ptr = (VOID *) a3;
; TMD_HISR_Stack_Size = TIMER_SIZE;
; TMD_HISR_Priority = TIMER_PRIORITY;
;
;LDR a4,[pc,#HISR_Stack_Ptr-.-8] ; Pickup variable's address
LDR a4,=HISR_Stack_Ptr
LDR a4,[a4,#0]
ADD a3,a3,#4 ; Increment to next available word
STR a3,[a4, #0] ; Setup timer HISR stack pointer
MOV a2,#TIMER_SIZE ; Pickup the timer HISR stack size
BIC a2,a2,#3 ; Insure word alignment
ADD a3,a3,a2 ; Allocate the timer HISR stack
; from available memory
;LDR a4,[pc,#HISR_Stack_Size-.-8] ; Pickup variable's address
LDR a4,=HISR_Stack_Size
LDR a4,[a4,#0]
STR a2,[a4, #0] ; Setup timer HISR stack size
MOV a2,#TIMER_PRIORITY ; Pickup timer HISR priority (0-2)
;LDR a4,[pc,#HISR_Priority-.-8] ; Pickup variable's address
LDR a4,=HISR_Priority
LDR a4,[a4,#0]
STR a2,[a4, #0] ; Setup timer HISR priority
;
; /* Setup the vectors loaded flag to indicate to other routines in the
; system whether or not all of the default vectors have been loaded.
; If INT_Loaded_Flag is 1, all of the default vectors have been loaded.
; Otherwise, if INT_Loaded_Flag is 0, registering an LISR cause the
; default vector to be loaded. In the ARM60 this variable is always
; set to 1. All vectors must be setup by this function. */
; INT_Loaded_Flag = 0;
;
MOV a1,#1 ; All vectors are assumed loaded
;LDR a2,[pc, #Loaded_Flag-.-8] ; Build address of loaded flag
LDR a2,=Loaded_Flag
LDR a2,[a2,#0]
STR a1,[a2,#0] ; Initialize loaded flag
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; /*
; Call INC_Initialize with a pointer to the first
; available memory address after the compiler's
; global data. This memory may be used by the
; application.
; */
; INC_Initialize(first_available_memory);
;
MOV a1,a3 ; Pass the first available memory
B INC_Initialize ; to high-level initialization
;}
;
;
;
;/*************************************************************************/
;/* */
;/* FUNCTION */
;/* */
;/* INT_Vectors_Loaded */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function returns the flag that indicates whether or not */
;/* all the default vectors have been loaded. If it is false, */
;/* each LISR register also loads the ISR shell into the actual */
;/* vector table. */
;/* */
;/* AUTHOR */
;/* */
;/* Gai, Feng, Watertek, Inc. */
;/* */
;/* CALLED BY */
;/* */
;/* TCC_Register_LISR Register LISR for vector */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* INPUTS */
;/* */
;/* None */
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