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;/*************************************************************************/
;/* */
;/* Copyright (c) 2002 - 2004 Digiway, Inc. */
;/* */
;/* PROPRIETARY RIGHTS of Watertek are involved in the subject matter of */
;/* this material. All manufacturing, reproduction, use, and sales */
;/* rights pertaining to this subject matter are governed by the license */
;/* agreement. The recipient of this software implicitly accepts the */
;/* terms of the license. */
;/* */
;/*************************************************************************/
;
;/*************************************************************************/
;/* */
;/* FILE NAME VERSION */
;/* */
;/* int.s KS32C41100 1.0 */
;/* */
;/* COMPONENT */
;/* */
;/* IN - Initialization */
;/* */
;/* DESCRIPTION */
;/* */
;/* This file contains the target processor dependent initialization */
;/* routines and data. */
;/* */
;/* AUTHOR */
;/* Gai, Feng, Watertek, Inc. */
;/* */
;/* DATA STRUCTURES */
;/* */
;/* INT_Vectors Interrupt vector table */
;/* */
;/* FUNCTIONS */
;/* */
;/* INT_Initialize Target initialization */
;/* INT_Vectors_Loaded Returns a NU_TRUE if all the */
;/* default vectors are loaded */
;/* INT_Setup_Vector Sets up an actual vector */
;/* */
;/* DEPENDENCIES */
;/* */
;/* nucleus.h System constants */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* */
;/* F. Gai 2000-04-03 Created initial version 1.0 */
;/* M. Chen 2002-07-12 Modified for 41100 */
;/* */
;/*************************************************************************/
;
;#include "nucleus.h" /* System constants */
;
;/* Vector Table Address at The Top of Memory */
EXPHDL_TBLBASE EQU 0x0c7fff00
;/* Interrupt Controller Register */
I_ISPR EQU 0x01e00020
I_ISPC EQU 0x01e00024
TIMER0_MASK_BIT EQU 0x00002000 ; bit 13 in INTMSK
;
;/* Define constants used in low-level initialization. */
;
;
LOCKOUT EQU &C0 ; Interrupt lockout value
LOCK_MSK EQU &C0 ; Interrupt lockout mask value
MODE_MASK EQU &1F ; Processor Mode Mask
SUP_MODE EQU &13 ; Supervisor Mode (SVC)
IRQ_MODE EQU &12 ; Interrupt Mode (IRQ)
FIQ_MODE EQU &11 ; Fast Interrupt Mode (FIQ)
I_BIT EQU 0x80 ; Interrupt bit of CPSR and SPSR
F_BIT EQU 0x40 ; Interrupt bit of CPSR and SPSR
;
; /* Constants used in NU+ */
;
IRQ_STACK_SIZE EQU 512 ; Number of bytes in IRQ stack
; -Note that the IRQ interrupt,
; by default, is managed by
; Nucleus PLUS. Only several
; words are actually used. The
; system stack is what will
; actually be used for Nuclues
; PLUS managed IRQ interrupts.
FIQ_STACK_SIZE EQU 512 ; Number of bytes in FIQ stack.
; This value is application
; specific. By default, Nucleus
; does not manage FIQ interrupts
; and furthermore, leaves them
; enabled virtually all the time.
SYSTEM_SIZE EQU 1024 ; Define the system stack size
TIMER_SIZE EQU 1024 ; Define timer HISR stack size
TIMER_PRIORITY EQU 2 ; Timer HISR priority (values from
; 0 to 2, where 0 is highest)
;
;/* End of low-level initialization constants. */
;
AREA |C$$data|,DATA
|x$dataseg|
;/* Define the initialization flag that indicates whether or not all of the
; default vectors have been loaded during initialization. */
;
;INT INT_Loaded_Flag;
EXPORT INT_Loaded_Flag
INT_Loaded_Flag
DCD &00000000
INT_Pending_Bit
DCD &00000000
AREA |C$$code|, CODE, READONLY
|x$codeseg|
;
;
;/* Define the global data structures that need to be initialized by this
; routine. These structures are used to define the system timer management
; HISR.
; */
;extern VOID *TMD_HISR_Stack_Ptr;
;extern UNSIGNED TMD_HISR_Stack_Size;
;extern INT TMD_HISR_Priority;
;
IMPORT TMD_HISR_Stack_Ptr
IMPORT TMD_HISR_Stack_Size
IMPORT TMD_HISR_Priority
;VOID TCT_Interrupt_Context_Save(VOID);
;VOID TCT_Interrupt_Context_Restore(VOID);
;VOID TCC_Dispatch_LISR(INT vector_number);
;VOID TMT_Timer_Interrupt(void);
;
IMPORT TCT_Interrupt_Context_Save
IMPORT TMT_Timer_Interrupt
IMPORT TCC_Dispatch_LISR
IMPORT TCT_Interrupt_Context_Restore
;/* Define the global system stack variable. This is setup by the
; initialization routine.
;*/
;extern VOID *TCD_System_Stack;
;
IMPORT TCD_System_Stack
IMPORT TCT_System_Limit
IMPORT INC_Initialize
IMPORT Board_Init
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
sub sp,sp,#4 ;decrement sp(to store jump address)
stmfd sp!,{r0} ;PUSH the work register to stack(lr does't push because it return to original address)
ldr r0,=$HandleLabel;load the address of HandleXXX to r0
ldr r0,[r0] ;load the contents(service routine start address) of HandleXXX
str r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stack
ldmfd sp!,{r0,pc} ;POP the work register and pc(jump to ISR)
MEND
;
;/* Define various data structure pointers so their addresses can be obtained
; in a PC-relative manner. */
;
B INT_Initialize
B HandlerUndef
B HandlerSWI
B HandlerPabort
B HandlerDabort
B . ; NO LONGER USED
B HandlerIRQ
B HandlerFIQ
LTORG
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
INT_Table
INT_Initialize_Addr DCD INT_Initialize
Undef_Instr_Addr DCD Undef_Instr_ISR
SWI_Addr DCD SWI_ISR
Prefetch_Abort_Addr DCD Prefetch_Abort_ISR
Data_Abort_Addr DCD Data_Abort_ISR
Undefined_Addr DCD 0 ; NO LONGER USED
IRQ_Handler_Addr DCD INT_IRQ_Parse
FIQ_Handler_Addr DCD INT_FIQ_Parse
Loaded_Flag
DCD INT_Loaded_Flag
;
HISR_Stack_Ptr
DCD TMD_HISR_Stack_Ptr
;
HISR_Stack_Size
DCD TMD_HISR_Stack_Size
;
HISR_Priority
DCD TMD_HISR_Priority
;
System_Stack
DCD TCD_System_Stack
;
System_Limit
DCD TCT_System_Limit
BSS_Start_Ptr
IMPORT |Image$$ZI$$Base|
DCD |Image$$ZI$$Base|
;
BSS_End_Ptr
IMPORT |Image$$ZI$$Limit|
DCD |Image$$ZI$$Limit|
;
ROM_Data_Start_Ptr
IMPORT |Image$$RO$$Limit|
DCD |Image$$RO$$Limit|
;
RAM_Start_Ptr
IMPORT |Image$$RW$$Base|
DCD |Image$$RW$$Base|
;
;
OLD_UNDEF_VECT
DCD &00000000
;
OLD_UNDEF_ADDR
DCD &00000000
;
OLD_SWI_VECT
DCD &00000000
;
OLD_SWI_ADDR
DCD &00000000
;
OLD_IRQ_VECT
DCD &00000000
;
OLD_IRQ_ADDR
DCD &00000000
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