pld01a.pnx

来自「Liod平台CPLD源代码 pxa270」· PNX 代码 · 共 19 行

<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
  arch   CDATA #REQUIRED
  device CDATA #REQUIRED
  spg    CDATA #REQUIRED
  pkg    CDATA #REQUIRED>
<!ATTLIST pin
  nm     CDATA #REQUIRED
  no     CDATA #REQUIRED
  iostd  (LVTTL|SSTL3_I|LVCMOS33|LVCMOS25|SSTL2_I|LVCMOS18|LVCMOS15|HSTL_I|NA) "NA"
  sr     (SLOW|FAST|slow|fast) "SLOW"
  dir    (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part pkg="TQ144" spg="-7" arch="xbr" device="XC2C256"/><pin nm="ADDR25" no="13" dir="input" iostd="LVCMOS18"/><pin nm="ADDR&lt;2&gt;" no="14" dir="input" iostd="LVCMOS18"/><pin nm="ADDR&lt;3&gt;" no="15" dir="input" iostd="LVCMOS18"/><pin nm="ADDR&lt;4&gt;" no="16" dir="input" iostd="LVCMOS18"/><pin nm="ADDR&lt;5&gt;" no="17" dir="input" iostd="LVCMOS18"/><pin nm="ADDR&lt;6&gt;" no="18" dir="input" iostd="LVCMOS18"/><pin nm="ADDR&lt;7&gt;" no="112" dir="input" iostd="LVCMOS18"/><pin nm="ADDR&lt;8&gt;" no="113" dir="input" iostd="LVCMOS18"/><pin nm="MBGNT" no="111" dir="input" iostd="LVCMOS18"/><pin nm="WEn" no="103" dir="input" iostd="LVCMOS18"/><pin nm="RD_WRn" no="105" dir="input" iostd="LVCMOS18"/><pin nm="CS2n" no="116" dir="input" iostd="LVCMOS18"/><pin nm="RESET_OUTn" no="87" dir="input" iostd="LVCMOS33"/><pin nm="OEn" no="110" dir="input" iostd="LVCMOS18"/><pin nm="CS5n" no="119" dir="input" iostd="LVCMOS18"/><pin nm="CF_BVD1" no="81" dir="input" iostd="LVCMOS33"/><pin nm="CF_BVD2" no="82" dir="input" iostd="LVCMOS33"/><pin nm="CF_CD1n" no="74" dir="input" iostd="LVCMOS33"/><pin nm="CF_CD2n" no="71" dir="input" iostd="LVCMOS33"/><pin nm="PCE2n" no="106" dir="input" iostd="LVCMOS18"/><pin nm="PCE1n" no="107" dir="input" iostd="LVCMOS18"/><pin nm="MMC_DETECT" no="61" dir="input" iostd="LVCMOS33"/><pin nm="SIM_DETECTn" no="88" dir="input" iostd="LVCMOS33"/><pin nm="SW1" no="91" dir="input" iostd="LVCMOS33"/><pin nm="SW2" no="92" dir="input" iostd="LVCMOS33"/><pin nm="SW3" no="60" dir="input" iostd="LVCMOS33"/><pin nm="SW4_1" no="59" dir="input" iostd="LVCMOS33"/><pin nm="SW4_2" no="58" dir="input" iostd="LVCMOS33"/><pin nm="SW4_3" no="57" dir="input" iostd="LVCMOS33"/><pin nm="USB1_WAKE" no="53" dir="input" iostd="LVCMOS33"/><pin nm="CS0n" no="114" dir="input" iostd="LVCMOS18"/><pin nm="CS1n" no="115" dir="input" iostd="LVCMOS18"/><pin nm="CS3n" no="117" dir="input" iostd="LVCMOS18"/><pin nm="CS4n" no="118" dir="input" iostd="LVCMOS18"/><pin nm="EX_IN1" no="64" dir="input" iostd="LVCMOS33"/><pin nm="POLL_FLAG" no="86" dir="input" iostd="LVCMOS33"/><pin nm="SWAP_FLASH" no="56" dir="input" iostd="LVCMOS33"/><pin nm="DVAL1" no="69" dir="input" iostd="LVCMOS33"/><pin nm="DIP_DATA" no="70" dir="input" iostd="LVCMOS33"/><pin nm="EXB_PRESn" no="68" dir="input" iostd="LVCMOS33"/><pin nm="EX_IN0" no="66" dir="input" iostd="LVCMOS33"/><pin nm="MMC_WP" no="83" dir="input" iostd="LVCMOS33"/><pin nm="MSINS" no="85" dir="input" iostd="LVCMOS33"/><pin nm="TX_IN0" no="104" dir="input" iostd="LVCMOS18"/><pin nm="TX_IN1" no="54" dir="input" iostd="LVCMOS33"/><pin nm="ADDR_DIRn" no="77" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="ADDR_OEn" no="49" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="AUDIO_PWR_EN" no="32" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="BRDY_ENn" no="133" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="CF_OEn" no="38" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="CF_PWR_EN" no="75" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="CF_RESET" no="31" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="CPLD_INTn" no="33" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="DAC_PWR_EN" no="28" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="DATA_DIRn" no="34" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="DATA_OEn" no="50" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="EX_FLASH_CSn" no="35" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="EX_OUT0" no="39" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="EX_OUT1" no="41" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="EX_REG_CSn" no="45" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="FLASH_CSn" no="10" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="FLASH_RSTn" no="11" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="HDD_PWR_EN" no="40" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="IRDA_FSEL" no="43" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="IRDA_MD0" no="26" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="IRDA_MD1" no="25" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="LAN_AEN" no="51" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="LAN_RESET" no="46" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="LCD_PWR_ON" no="42" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="LED_GREENn" no="24" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="LED_REDn" no="23" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="MMC_PWR_EN" no="78" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="MS_PULL" no="79" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="MS_PWR_EN" no="80" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="PSKTSEL" no="22" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="RS232_ON" no="21" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="SLEEPn" no="20" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="SPKR_OFF" no="19" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="SYS_CS0n" no="132" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="SYS_CS1n" no="131" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="TX_OUT0" no="12" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="TX_OUT1" no="52" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="USB_IDE_CSn" no="76" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="USB_IDE_RESn" no="48" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="VBUS1_ON" no="30" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="VGA_I2C_ENn" no="44" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="DATA&lt;12&gt;" no="3" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;1&gt;" no="2" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;2&gt;" no="7" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;3&gt;" no="9" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;7&gt;" no="4" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;8&gt;" no="5" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;9&gt;" no="6" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;0&gt;" no="143" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;15&gt;" no="140" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;5&gt;" no="135" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;10&gt;" no="138" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;11&gt;" no="137" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;13&gt;" no="139" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;14&gt;" no="142" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;4&gt;" no="136" sr="fast" dir="bidir" iostd="LVCMOS18"/><pin nm="DATA&lt;6&gt;" no="134" sr="fast" dir="bidir" iostd="LVCMOS18"/></ibis>