pld01a.mfd

Liod平台CPLD源代码 pxa270

   VBUS1_ON := DATA<1>.PIN;
    VBUS1_ON.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    VBUS1_ON.AR = !RESET_OUTn;

MACROCELL | 1 | 12 | DATA<2>_MC
ATTRIBUTES | 1141113602 | 2
INPUTS | 8 | N_PZ_261  | SIM_IN_INT  | ADDR<3>  | ADDR<2>  | SW3  | CF_BVD2  | VGA_I2C_ENn  | IRDA_FSEL
INPUTMC | 4 | 3 | 3 | 2 | 9 | 7 | 0 | 5 | 15
INPUTP | 4 | 19 | 18 | 90 | 121
LCT | 1 | 5 | Internal_Name
EQ | 6 | 
   DATA<2> = !N_PZ_261 * SIM_IN_INT
	# ADDR<3> * ADDR<2> * N_PZ_261 * SW3
	# ADDR<3> * !ADDR<2> * N_PZ_261 * CF_BVD2
	# !ADDR<3> * ADDR<2> * N_PZ_261 * VGA_I2C_ENn
	# !ADDR<3> * !ADDR<2> * N_PZ_261 * IRDA_FSEL;
    DATA<2>.OE = _n0051;

MACROCELL | 5 | 15 | IRDA_FSEL_MC
ATTRIBUTES | 2290352914 | 0
OUTPUTMC | 1 | 1 | 12
INPUTS | 2 | DATA<2>.PIN  | RESET_OUTn
INPUTP | 2 | 8 | 133
LCT | 1 | 2 | Internal_Name
EQ | 5 | 
   IRDA_FSEL := DATA<2>.PIN;
    IRDA_FSEL.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    IRDA_FSEL.AR = !RESET_OUTn;

MACROCELL | 7 | 0 | VGA_I2C_ENn_MC
ATTRIBUTES | 2156135218 | 0
OUTPUTMC | 1 | 1 | 12
INPUTS | 13 | DATA<2>.PIN  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | RESET_OUTn
INPUTP | 13 | 8 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 133
EQ | 5 | 
   VGA_I2C_ENn := DATA<2>.PIN;
    VGA_I2C_ENn.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    VGA_I2C_ENn.AR = !RESET_OUTn;

MACROCELL | 1 | 13 | DATA<3>_MC
ATTRIBUTES | 1141113602 | 2
INPUTS | 8 | N_PZ_261  | SIM_OUT_INT  | ADDR<3>  | ADDR<2>  | SW4_1  | MMC_DETECT  | DAC_PWR_EN  | IRDA_MD0
INPUTMC | 4 | 3 | 3 | 2 | 7 | 4 | 13 | 6 | 4
INPUTP | 4 | 19 | 18 | 89 | 95
LCT | 1 | 5 | Internal_Name
EQ | 6 | 
   DATA<3> = !N_PZ_261 * SIM_OUT_INT
	# ADDR<3> * ADDR<2> * N_PZ_261 * SW4_1
	# ADDR<3> * !ADDR<2> * N_PZ_261 * MMC_DETECT
	# !ADDR<3> * ADDR<2> * N_PZ_261 * DAC_PWR_EN
	# !ADDR<3> * !ADDR<2> * N_PZ_261 * IRDA_MD0;
    DATA<3>.OE = _n0051;

MACROCELL | 6 | 4 | IRDA_MD0_MC
ATTRIBUTES | 2290352914 | 0
OUTPUTMC | 1 | 1 | 13
INPUTS | 2 | DATA<3>.PIN  | RESET_OUTn
INPUTP | 2 | 10 | 133
LCT | 1 | 2 | Internal_Name
EQ | 5 | 
   IRDA_MD0 := DATA<3>.PIN;
    IRDA_MD0.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    IRDA_MD0.AR = !RESET_OUTn;

MACROCELL | 1 | 3 | DATA<7>_MC
ATTRIBUTES | 1141113602 | 2
INPUTS | 7 | N_PZ_261  | CF_OUT_INT  | ADDR<3>  | ADDR<2>  | POLL_FLAG  | BCR2_REG<7>  | HDD_PWR_EN
INPUTMC | 4 | 3 | 3 | 5 | 9 | 9 | 15 | 5 | 12
INPUTP | 3 | 19 | 18 | 132
LCT | 1 | 5 | Internal_Name
EQ | 5 | 
   DATA<7> = !N_PZ_261 * CF_OUT_INT
	# ADDR<3> * !ADDR<2> * N_PZ_261 * POLL_FLAG
	# !ADDR<3> * ADDR<2> * N_PZ_261 * BCR2_REG<7>
	# !ADDR<3> * !ADDR<2> * N_PZ_261 * HDD_PWR_EN;
    DATA<7>.OE = _n0051;

MACROCELL | 5 | 12 | HDD_PWR_EN_MC
ATTRIBUTES | 2290352914 | 0
OUTPUTMC | 1 | 1 | 3
INPUTS | 2 | DATA<7>.PIN  | RESET_OUTn
INPUTP | 2 | 4 | 133
LCT | 1 | 2 | Internal_Name
EQ | 5 | 
   HDD_PWR_EN := DATA<7>.PIN;
    HDD_PWR_EN.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    HDD_PWR_EN.AR = !RESET_OUTn;

MACROCELL | 9 | 15 | BCR2_REG<7>_MC
ATTRIBUTES | 2323645184 | 0
OUTPUTMC | 1 | 1 | 3
INPUTS | 1 | DATA<7>.PIN
INPUTP | 1 | 4
LCT | 2 | 4 | Internal_Name | 2 | Internal_Name
EQ | 5 | 
   BCR2_REG<7> := DATA<7>.PIN;
    BCR2_REG<7>.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    BCR2_REG<7>.AR = !RESET_OUTn;

MACROCELL | 1 | 4 | DATA<8>_MC
ATTRIBUTES | 1141113602 | 2
INPUTS | 7 | N_PZ_261  | SW1_INT  | ADDR<3>  | ADDR<2>  | USB1_WAKE  | EX_OUT1  | LCD_PWR_ON
INPUTMC | 4 | 3 | 3 | 5 | 10 | 5 | 13 | 5 | 14
INPUTP | 3 | 19 | 18 | 81
LCT | 1 | 5 | Internal_Name
EQ | 5 | 
   DATA<8> = !N_PZ_261 * SW1_INT
	# ADDR<3> * !ADDR<2> * N_PZ_261 * USB1_WAKE
	# !ADDR<3> * ADDR<2> * N_PZ_261 * EX_OUT1
	# !ADDR<3> * !ADDR<2> * N_PZ_261 * LCD_PWR_ON;
    DATA<8>.OE = _n0051;

MACROCELL | 5 | 14 | LCD_PWR_ON_MC
ATTRIBUTES | 2290352914 | 0
OUTPUTMC | 1 | 1 | 4
INPUTS | 2 | DATA<8>.PIN  | RESET_OUTn
INPUTP | 2 | 5 | 133
LCT | 1 | 2 | Internal_Name
EQ | 5 | 
   LCD_PWR_ON := DATA<8>.PIN;
    LCD_PWR_ON.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    LCD_PWR_ON.AR = !RESET_OUTn;

MACROCELL | 5 | 13 | EX_OUT1_MC
ATTRIBUTES | 2156135218 | 0
OUTPUTMC | 1 | 1 | 4
INPUTS | 13 | DATA<8>.PIN  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | RESET_OUTn
INPUTP | 13 | 5 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 133
EQ | 5 | 
   EX_OUT1 := DATA<8>.PIN;
    EX_OUT1.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    EX_OUT1.AR = !RESET_OUTn;

MACROCELL | 1 | 11 | DATA<9>_MC
ATTRIBUTES | 1141113602 | 2
INPUTS | 7 | N_PZ_261  | SW2_INT  | ADDR<3>  | ADDR<2>  | SWAP_FLASH  | BCR2_REG<9>  | RS232_ON
INPUTMC | 4 | 3 | 3 | 3 | 11 | 10 | 4 | 6 | 13
INPUTP | 3 | 19 | 18 | 86
LCT | 1 | 5 | Internal_Name
EQ | 5 | 
   DATA<9> = !N_PZ_261 * SW2_INT
	# ADDR<3> * !ADDR<2> * N_PZ_261 * SWAP_FLASH
	# !ADDR<3> * ADDR<2> * N_PZ_261 * BCR2_REG<9>
	# !ADDR<3> * !ADDR<2> * N_PZ_261 * RS232_ON;
    DATA<9>.OE = _n0051;

MACROCELL | 6 | 13 | RS232_ON_MC
ATTRIBUTES | 2290353026 | 0
OUTPUTMC | 1 | 1 | 11
INPUTS | 2 | DATA<9>.PIN  | RESET_OUTn
INPUTP | 2 | 7 | 133
LCT | 1 | 2 | Internal_Name
EQ | 5 | 
   RS232_ON := DATA<9>.PIN;
    RS232_ON.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    RS232_ON.AP = !RESET_OUTn;

MACROCELL | 5 | 0 | DATA_DIRn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 13 | RD_WRn  | PCE2n  | PCE1n  | CS4n  | CS3n  | BCR2_REG<4>  | OEn  | ADDR25  | CS2n  | SWAP_FLASH  | CS0n  | DVAL1  | BCR2_REG<5>
INPUTMC | 2 | 2 | 0 | 3 | 6
INPUTP | 11 | 161 | 162 | 163 | 177 | 176 | 166 | 17 | 175 | 86 | 171 | 107
EQ | 9 | 
   !DATA_DIRn = RD_WRn * !PCE2n
	# RD_WRn * !PCE1n
	# RD_WRn * !CS4n
	# RD_WRn * !CS3n
	# BCR2_REG<4> * RD_WRn * OEn
	# !ADDR25 * RD_WRn * !CS2n
	# RD_WRn * !CS2n * OEn
	# RD_WRn * SWAP_FLASH * !CS0n
	# RD_WRn * !DVAL1 * BCR2_REG<5>;

MACROCELL | 3 | 6 | BCR2_REG<5>_MC
ATTRIBUTES | 2290090768 | 0
OUTPUTMC | 2 | 5 | 0 | 2 | 1
INPUTS | 2 | DATA<5>.PIN  | RESET_OUTn
INPUTP | 2 | 207 | 133
LCT | 1 | 2 | Internal_Name
EQ | 5 | 
   BCR2_REG<5> := DATA<5>.PIN;
    BCR2_REG<5>.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    BCR2_REG<5>.AR = !RESET_OUTn;

MACROCELL | 7 | 10 | DATA_OEn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 0
EQ | 1 | 
   DATA_OEn = Gnd;

MACROCELL | 5 | 1 | EX_FLASH_CSn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 2 | SWAP_FLASH  | CS0n
INPUTP | 2 | 86 | 171
EQ | 1 | 
   !EX_FLASH_CSn = SWAP_FLASH * !CS0n;

MACROCELL | 5 | 11 | EX_OUT0_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 2 | ADDR25  | CS2n
INPUTP | 2 | 17 | 175
EQ | 1 | 
   !EX_OUT0 = !ADDR25 * !CS2n;

MACROCELL | 7 | 1 | EX_REG_CSn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 2 | ADDR25  | CS2n
INPUTP | 2 | 17 | 175
EQ | 1 | 
   !EX_REG_CSn = !ADDR25 * !CS2n;

MACROCELL | 1 | 14 | FLASH_CSn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 2 | SWAP_FLASH  | CS0n
INPUTP | 2 | 86 | 171
EQ | 1 | 
   !FLASH_CSn = !SWAP_FLASH * !CS0n;

MACROCELL | 3 | 0 | FLASH_RSTn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 1 | RESET_OUTn
INPUTP | 1 | 133
EQ | 1 | 
   FLASH_RSTn = RESET_OUTn;

MACROCELL | 6 | 5 | IRDA_MD1_MC
ATTRIBUTES | 2290353026 | 0
OUTPUTMC | 1 | 2 | 0
INPUTS | 2 | DATA<4>.PIN  | RESET_OUTn
INPUTP | 2 | 208 | 133
LCT | 1 | 2 | Internal_Name
EQ | 5 | 
   IRDA_MD1 := DATA<4>.PIN;
    IRDA_MD1.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    IRDA_MD1.AP = !RESET_OUTn;

MACROCELL | 7 | 11 | LAN_AEN_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 1 | CS3n
INPUTP | 1 | 176
EQ | 1 | 
   LAN_AEN = CS3n;

MACROCELL | 7 | 2 | LAN_RESET_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 1 | RESET_OUTn
INPUTP | 1 | 133
EQ | 1 | 
   LAN_RESET = !RESET_OUTn;

MACROCELL | 6 | 10 | LED_GREENn_MC
ATTRIBUTES | 2290353026 | 0
OUTPUTMC | 1 | 0 | 11
INPUTS | 2 | DATA<13>.PIN  | RESET_OUTn
INPUTP | 2 | 213 | 133
LCT | 1 | 2 | Internal_Name
EQ | 5 | 
   LED_GREENn := DATA<13>.PIN;
    LED_GREENn.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    LED_GREENn.AP = !RESET_OUTn;

MACROCELL | 12 | 4 | MMC_PWR_EN_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 2 | MMC_DETECT  | BCR1_REG<15>
INPUTMC | 1 | 0 | 5
INPUTP | 1 | 95
EQ | 1 | 
   MMC_PWR_EN = MMC_DETECT * BCR1_REG<15>;

MACROCELL | 0 | 5 | BCR1_REG<15>_MC
ATTRIBUTES | 3330540322 | 6
OUTPUTMC | 3 | 12 | 4 | 12 | 5 | 0 | 5
INPUTS | 14 | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | N_PZ_261  | BCR2_REG<15>  | BCR1_REG<15>
INPUTMC | 3 | 3 | 3 | 3 | 13 | 0 | 5
INPUTP | 11 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169
LCT | 2 | 4 | Internal_Name | 5 | Internal_Name
EQ | 9 | 
   DATA<15> =  !ADDR<3> * ADDR<2> * N_PZ_261 * BCR2_REG<15>
	# !ADDR<3> * !ADDR<2> * N_PZ_261 * BCR1_REG<15>;
    DATA<15>.OE = _n0051;
// Direct Input Register
BCR1_REG<15> := DATA<15>.PIN;
    BCR1_REG<15>.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    BCR1_REG<15>.AR = !RESET_OUTn;

MACROCELL | 12 | 5 | MS_PULL_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 2 | MMC_DETECT  | BCR1_REG<15>
INPUTMC | 1 | 0 | 5
INPUTP | 1 | 95
EQ | 1 | 
   !MS_PULL = MMC_DETECT * !BCR1_REG<15>;