📄 pld01a.mfd
字号:
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 10
EQ | 4 |
SIM_OUT_INT__n0000 = !RESET_OUTn
# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<3>.PIN;
MACROCELL | 5 | 10 | SW1_INT_MC
ATTRIBUTES | 2172650288 | 0
OUTPUTMC | 2 | 4 | 1 | 1 | 4
INPUTS | 14 | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<8>.PIN | SW1 | SW1_INT__n0000
INPUTMC | 1 | 2 | 6
INPUTP | 13 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 5 | 137
LCT | 1 | 1 | Internal_Name
EQ | 8 |
!SW1_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<8>.PIN;
SW1_INT.CLK = !(SW1);
SW1_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * DATA<8>.PIN;
SW1_INT.AR = SW1_INT__n0000;
MACROCELL | 2 | 6 | SW1_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
OUTPUTMC | 1 | 5 | 10
INPUTS | 13 | RESET_OUTn | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<8>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 5
EQ | 4 |
SW1_INT__n0000 = !RESET_OUTn
# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<8>.PIN;
MACROCELL | 3 | 11 | SW2_INT_MC
ATTRIBUTES | 2172650288 | 0
OUTPUTMC | 2 | 4 | 1 | 1 | 11
INPUTS | 14 | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<9>.PIN | SW2 | SW2_INT__n0000
INPUTMC | 1 | 3 | 15
INPUTP | 13 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 7 | 138
LCT | 1 | 1 | Internal_Name
EQ | 8 |
!SW2_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<9>.PIN;
SW2_INT.CLK = !(SW2);
SW2_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * DATA<9>.PIN;
SW2_INT.AR = SW2_INT__n0000;
MACROCELL | 3 | 15 | SW2_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
OUTPUTMC | 1 | 3 | 11
INPUTS | 13 | RESET_OUTn | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<9>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 7
EQ | 4 |
SW2_INT__n0000 = !RESET_OUTn
# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<9>.PIN;
MACROCELL | 3 | 5 | SW3_INT_MC
ATTRIBUTES | 2189427616 | 0
OUTPUTMC | 2 | 4 | 1 | 0 | 12
INPUTS | 13 | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<10>.PIN | SW3
INPUTP | 13 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 212 | 90
LCT | 1 | 4 | Internal_Name
EQ | 8 |
!SW3_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<10>.PIN;
SW3_INT.CLK = !(SW3);
SW3_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * DATA<10>.PIN;
SW3_INT.AR = SW3_INT__n0000;
MACROCELL | 3 | 14 | SW3_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
INPUTS | 13 | RESET_OUTn | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<10>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 212
EQ | 4 |
SW3_INT__n0000 = !RESET_OUTn
# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<10>.PIN;
MACROCELL | 6 | 9 | SW4_1INT_MC
ATTRIBUTES | 2189427616 | 0
OUTPUTMC | 2 | 4 | 1 | 0 | 13
INPUTS | 13 | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<11>.PIN | SW4_1
INPUTP | 13 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 211 | 89
LCT | 1 | 4 | Internal_Name
EQ | 8 |
!SW4_1INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<11>.PIN;
SW4_1INT.CLK = !(SW4_1);
SW4_1INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * DATA<11>.PIN;
SW4_1INT.AR = SW4_1INT__n0000;
MACROCELL | 3 | 12 | SW4_1INT__n0000_MC
ATTRIBUTES | 536871680 | 0
INPUTS | 13 | RESET_OUTn | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<11>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 211
EQ | 4 |
SW4_1INT__n0000 = !RESET_OUTn
# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<11>.PIN;
MACROCELL | 6 | 8 | SW4_2INT_MC
ATTRIBUTES | 2172650288 | 0
OUTPUTMC | 2 | 4 | 1 | 1 | 2
INPUTS | 14 | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<12>.PIN | SW4_2 | SW4_2INT__n0000
INPUTMC | 1 | 3 | 10
INPUTP | 13 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 3 | 88
LCT | 1 | 1 | Internal_Name
EQ | 8 |
!SW4_2INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<12>.PIN;
SW4_2INT.CLK = !(SW4_2);
SW4_2INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * DATA<12>.PIN;
SW4_2INT.AR = SW4_2INT__n0000;
MACROCELL | 3 | 10 | SW4_2INT__n0000_MC
ATTRIBUTES | 536871680 | 0
OUTPUTMC | 1 | 6 | 8
INPUTS | 13 | RESET_OUTn | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<12>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 3
EQ | 4 |
SW4_2INT__n0000 = !RESET_OUTn
# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<12>.PIN;
MACROCELL | 7 | 15 | SW4_3INT_MC
ATTRIBUTES | 2172650288 | 0
OUTPUTMC | 2 | 4 | 1 | 0 | 11
INPUTS | 14 | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<13>.PIN | SW4_3 | SW4_3INT__n0000
INPUTMC | 1 | 3 | 9
INPUTP | 13 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 213 | 87
LCT | 1 | 1 | Internal_Name
EQ | 8 |
!SW4_3INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<13>.PIN;
SW4_3INT.CLK = !(SW4_3);
SW4_3INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * DATA<13>.PIN;
SW4_3INT.AR = SW4_3INT__n0000;
MACROCELL | 3 | 9 | SW4_3INT__n0000_MC
ATTRIBUTES | 536871680 | 0
OUTPUTMC | 1 | 7 | 15
INPUTS | 13 | RESET_OUTn | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<13>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 213
EQ | 4 |
SW4_3INT__n0000 = !RESET_OUTn
# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<13>.PIN;
MACROCELL | 7 | 14 | USB_IN_INT_MC
ATTRIBUTES | 2323645312 | 0
OUTPUTMC | 2 | 4 | 1 | 2 | 0
INPUTS | 12 | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<4>.PIN
INPUTP | 12 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 208
LCT | 2 | 4 | Internal_Name | 2 | Internal_Name
EQ | 8 |
!USB_IN_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<4>.PIN;
USB_IN_INT.CLK = USB1_WAKE;
USB_IN_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * DATA<4>.PIN;
USB_IN_INT.AR = USB_IN_INT__n0000;
MACROCELL | 3 | 8 | USB_IN_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
INPUTS | 13 | RESET_OUTn | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<4>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 208
EQ | 4 |
USB_IN_INT__n0000 = !RESET_OUTn
# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<4>.PIN;
MACROCELL | 8 | 15 | USB_OUT_INT_MC
ATTRIBUTES | 2340422400 | 0
OUTPUTMC | 2 | 4 | 1 | 2 | 1
INPUTS | 12 | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<5>.PIN
INPUTP | 12 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 207
LCT | 3 | 1 | Internal_Name | 4 | Internal_Name | 2 | Internal_Name
EQ | 8 |
!USB_OUT_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<5>.PIN;
USB_OUT_INT.CLK = !(USB1_WAKE);
USB_OUT_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * DATA<5>.PIN;
USB_OUT_INT.AR = USB_OUT_INT__n0000;
MACROCELL | 3 | 7 | USB_OUT_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
INPUTS | 13 | RESET_OUTn | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | DATA<5>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 207
EQ | 4 |
USB_OUT_INT__n0000 = !RESET_OUTn
# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8> * !DATA<5>.PIN;
MACROCELL | 10 | 4 | BCR2_REG<9>_MC
ATTRIBUTES | 2306867968 | 0
OUTPUTMC | 2 | 4 | 1 | 1 | 11
INPUTS | 1 | DATA<9>.PIN
INPUTP | 1 | 7
LCT | 2 | 1 | Internal_Name | 2 | Internal_Name
EQ | 5 |
BCR2_REG<9> := DATA<9>.PIN;
BCR2_REG<9>.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
!ADDR<4> * !ADDR<3> * ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8>);
BCR2_REG<9>.AP = !RESET_OUTn;
MACROCELL | 3 | 2 | _n002215_MC
ATTRIBUTES | 536871680 | 0
OUTPUTMC | 1 | 4 | 1
INPUTS | 16 | DATA<6>.PIN | DATA<1>.PIN | DATA<7>.PIN | DATA<0>.PIN | DATA<2>.PIN | DATA<3>.PIN | DATA<8>.PIN | DATA<9>.PIN | DATA<10>.PIN | DATA<11>.PIN | DATA<12>.PIN | DATA<13>.PIN | DATA<4>.PIN | DATA<5>.PIN | DATA<15>.PIN | DATA<14>.PIN
INPUTP | 16 | 206 | 1 | 4 | 218 | 8 | 10 | 5 | 7 | 212 | 211 | 3 | 213 | 208 | 207 | 214 | 217
EQ | 5 |
_n002215 = DATA<6>.PIN * DATA<1>.PIN * DATA<7>.PIN *
DATA<0>.PIN * DATA<2>.PIN * DATA<3>.PIN * DATA<8>.PIN *
DATA<9>.PIN * DATA<10>.PIN * DATA<11>.PIN * DATA<12>.PIN *
DATA<13>.PIN * DATA<4>.PIN * DATA<5>.PIN * DATA<15>.PIN *
DATA<14>.PIN;
MACROCELL | 4 | 13 | DAC_PWR_EN_MC
ATTRIBUTES | 2156135218 | 0
OUTPUTMC | 1 | 1 | 13
INPUTS | 13 | DATA<3>.PIN | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | RESET_OUTn
INPUTP | 13 | 10 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 133
EQ | 5 |
DAC_PWR_EN := DATA<3>.PIN;
DAC_PWR_EN.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
!ADDR<4> * !ADDR<3> * ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8>);
DAC_PWR_EN.AR = !RESET_OUTn;
MACROCELL | 1 | 2 | DATA<12>_MC
ATTRIBUTES | 1141113602 | 2
INPUTS | 7 | N_PZ_261 | SW4_2INT | ADDR<3> | ADDR<2> | EX_IN1 | BCR2_REG<12> | LED_REDn
INPUTMC | 4 | 3 | 3 | 6 | 8 | 9 | 13 | 6 | 11
INPUTP | 3 | 19 | 18 | 100
LCT | 1 | 5 | Internal_Name
EQ | 5 |
DATA<12> = !N_PZ_261 * SW4_2INT
# ADDR<3> * !ADDR<2> * N_PZ_261 * EX_IN1
# !ADDR<3> * ADDR<2> * N_PZ_261 * BCR2_REG<12>
# !ADDR<3> * !ADDR<2> * N_PZ_261 * LED_REDn;
DATA<12>.OE = _n0051;
MACROCELL | 6 | 11 | LED_REDn_MC
ATTRIBUTES | 2290353026 | 0
OUTPUTMC | 1 | 1 | 2
INPUTS | 2 | DATA<12>.PIN | RESET_OUTn
INPUTP | 2 | 3 | 133
LCT | 1 | 2 | Internal_Name
EQ | 5 |
LED_REDn := DATA<12>.PIN;
LED_REDn.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8>);
LED_REDn.AP = !RESET_OUTn;
MACROCELL | 9 | 13 | BCR2_REG<12>_MC
ATTRIBUTES | 2323645184 | 0
OUTPUTMC | 1 | 1 | 2
INPUTS | 1 | DATA<12>.PIN
INPUTP | 1 | 3
LCT | 2 | 4 | Internal_Name | 2 | Internal_Name
EQ | 5 |
BCR2_REG<12> := DATA<12>.PIN;
BCR2_REG<12>.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> *
!ADDR<4> * !ADDR<3> * ADDR<2> * !ADDR<7> * !ADDR<6> *
!ADDR<8>);
BCR2_REG<12>.AR = !RESET_OUTn;
MACROCELL | 1 | 0 | DATA<1>_MC
ATTRIBUTES | 1141113602 | 2
INPUTS | 8 | N_PZ_261 | MMC_OUT_INT | ADDR<3> | ADDR<2> | SW2 | CF_BVD1 | VBUS1_ON | CF_RESET
INPUTMC | 4 | 3 | 3 | 4 | 15 | 4 | 5 | 4 | 4
INPUTP | 4 | 19 | 18 | 138 | 120
LCT | 1 | 5 | Internal_Name
EQ | 6 |
DATA<1> = !N_PZ_261 * MMC_OUT_INT
# ADDR<3> * ADDR<2> * N_PZ_261 * SW2
# ADDR<3> * !ADDR<2> * N_PZ_261 * CF_BVD1
# !ADDR<3> * ADDR<2> * N_PZ_261 * VBUS1_ON
# !ADDR<3> * !ADDR<2> * N_PZ_261 * CF_RESET;
DATA<1>.OE = _n0051;
MACROCELL | 4 | 5 | VBUS1_ON_MC
ATTRIBUTES | 2156135218 | 0
OUTPUTMC | 1 | 1 | 0
INPUTS | 13 | DATA<1>.PIN | ADDR25 | WEn | RD_WRn | CS2n | ADDR<5> | ADDR<4> | ADDR<3> | ADDR<2> | ADDR<7> | ADDR<6> | ADDR<8> | RESET_OUTn
INPUTP | 13 | 1 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 133
EQ | 5 |
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