pld01a.mfd

Liod平台CPLD源代码 pxa270

MDF Database:  version 1.0
MDF_INFO | pld01a | XC2C256-7-TQ144
MACROCELL | 12 | 2 | ADDR_DIRn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 2 | MBGNT  | BCR2_REG<4>
INPUTMC | 1 | 2 | 0
INPUTP | 1 | 167
EQ | 1 | 
   !ADDR_DIRn = MBGNT * BCR2_REG<4>;

MACROCELL | 2 | 0 | BCR2_REG<4>_MC
ATTRIBUTES | 3431203602 | 6
OUTPUTMC | 3 | 12 | 2 | 5 | 0 | 2 | 0
INPUTS | 9 | RESET_OUTn  | N_PZ_261  | USB_IN_INT  | BCR2_REG<4>  | ADDR<3>  | ADDR<2>  | SW4_2  | MMC_WP  | IRDA_MD1
INPUTMC | 4 | 3 | 3 | 7 | 14 | 2 | 0 | 6 | 5
INPUTP | 5 | 133 | 19 | 18 | 88 | 125
LCT | 2 | 2 | Internal_Name | 5 | Internal_Name
EQ | 12 | 
   DATA<4> =  !N_PZ_261 * USB_IN_INT
	# BCR2_REG<4> * !ADDR<3> * ADDR<2> * N_PZ_261
	# ADDR<3> * ADDR<2> * N_PZ_261 * SW4_2
	# ADDR<3> * !ADDR<2> * N_PZ_261 * MMC_WP
	# !ADDR<3> * !ADDR<2> * N_PZ_261 * IRDA_MD1;
    DATA<4>.OE = _n0051;
// Direct Input Register
BCR2_REG<4> := DATA<4>.PIN;
    BCR2_REG<4>.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    BCR2_REG<4>.AR = !RESET_OUTn;

MACROCELL | 3 | 4 | _n0051_MC
ATTRIBUTES | 536871680 | 0
INPUTS | 11 | N_PZ_261  | ADDR25  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | OEn
INPUTMC | 1 | 3 | 3
INPUTP | 10 | 17 | 161 | 175 | 21 | 19 | 18 | 168 | 23 | 169 | 166
EQ | 3 | 
   _n0051 = N_PZ_261
	# ADDR25 * RD_WRn * !CS2n * !ADDR<5> * !ADDR<3> * 
	!ADDR<2> * !ADDR<7> * !ADDR<6> * !ADDR<8> * !OEn;

MACROCELL | 3 | 3 | N_PZ_261_MC
ATTRIBUTES | 536871680 | 0
OUTPUTMC | 17 | 3 | 4 | 1 | 2 | 1 | 0 | 1 | 12 | 1 | 13 | 1 | 3 | 1 | 4 | 1 | 11 | 0 | 2 | 0 | 5 | 2 | 1 | 0 | 12 | 0 | 13 | 0 | 11 | 0 | 3 | 2 | 0 | 2 | 2
INPUTS | 9 | ADDR25  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | OEn
INPUTP | 9 | 17 | 161 | 175 | 21 | 20 | 168 | 23 | 169 | 166
EQ | 2 | 
   N_PZ_261 = ADDR25 * RD_WRn * !CS2n * !ADDR<5> * !ADDR<4> * 
	!ADDR<7> * !ADDR<6> * !ADDR<8> * !OEn;

MACROCELL | 7 | 5 | ADDR_OEn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 0
EQ | 1 | 
   ADDR_OEn = Gnd;

MACROCELL | 4 | 3 | AUDIO_PWR_EN_MC
ATTRIBUTES | 2156135218 | 0
OUTPUTMC | 1 | 2 | 2
INPUTS | 13 | DATA<6>.PIN  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | RESET_OUTn
INPUTP | 13 | 206 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 133
EQ | 5 | 
   AUDIO_PWR_EN := DATA<6>.PIN;
    AUDIO_PWR_EN.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    AUDIO_PWR_EN.AR = !RESET_OUTn;

MACROCELL | 2 | 4 | BRDY_ENn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 1 | CS5n
INPUTP | 1 | 178
EQ | 1 | 
   BRDY_ENn = !CS5n;

MACROCELL | 5 | 3 | CF_OEn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 3 | BCR1_REG<5>  | PCE2n  | PCE1n
INPUTMC | 1 | 2 | 1
INPUTP | 2 | 162 | 163
EQ | 2 | 
   CF_OEn = BCR1_REG<5>
	# PCE2n * PCE1n;

MACROCELL | 2 | 1 | BCR1_REG<5>_MC
ATTRIBUTES | 3296986018 | 6
OUTPUTMC | 2 | 5 | 3 | 2 | 1
INPUTS | 18 | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | RESET_OUTn  | N_PZ_261  | USB_OUT_INT  | SW4_3  | SIM_DETECTn  | BCR2_REG<5>  | BCR1_REG<5>
INPUTMC | 4 | 3 | 3 | 8 | 15 | 3 | 6 | 2 | 1
INPUTP | 14 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 133 | 87 | 134
LCT | 1 | 5 | Internal_Name
EQ | 12 | 
   DATA<5> =  !N_PZ_261 * USB_OUT_INT
	# ADDR<3> * ADDR<2> * N_PZ_261 * SW4_3
	# ADDR<3> * !ADDR<2> * N_PZ_261 * SIM_DETECTn
	# !ADDR<3> * ADDR<2> * N_PZ_261 * BCR2_REG<5>
	# !ADDR<3> * !ADDR<2> * N_PZ_261 * BCR1_REG<5>;
    DATA<5>.OE = _n0051;
// Direct Input Register
BCR1_REG<5> := DATA<5>.PIN;
    BCR1_REG<5>.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    BCR1_REG<5>.AP = !RESET_OUTn;

MACROCELL | 12 | 0 | CF_PWR_EN_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 3 | CF_CD2n  | CF_CD1n  | BCR1_REG<0>
INPUTMC | 1 | 0 | 2
INPUTP | 2 | 109 | 112
EQ | 1 | 
   CF_PWR_EN = !CF_CD2n * !CF_CD1n * BCR1_REG<0>;

MACROCELL | 0 | 2 | BCR1_REG<0>_MC
ATTRIBUTES | 3330540322 | 6
OUTPUTMC | 2 | 12 | 0 | 0 | 2
INPUTS | 18 | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | N_PZ_261  | MMC_IN_INT  | SW1  | BCR2_REG<0>  | BCR1_REG<0>  | CF_CD2n  | CF_CD1n
INPUTMC | 4 | 3 | 3 | 4 | 14 | 2 | 12 | 0 | 2
INPUTP | 14 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 137 | 109 | 112
LCT | 2 | 4 | Internal_Name | 5 | Internal_Name
EQ | 13 | 
   DATA<0> =  !N_PZ_261 * MMC_IN_INT
	# ADDR<3> * ADDR<2> * N_PZ_261 * SW1
	# !ADDR<3> * ADDR<2> * N_PZ_261 * BCR2_REG<0>
	# !ADDR<3> * !ADDR<2> * N_PZ_261 * BCR1_REG<0>
	# ADDR<3> * !ADDR<2> * N_PZ_261 * !CF_CD2n * 
	!CF_CD1n;
    DATA<0>.OE = _n0051;
// Direct Input Register
BCR1_REG<0> := DATA<0>.PIN;
    BCR1_REG<0>.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    BCR1_REG<0>.AR = !RESET_OUTn;

MACROCELL | 4 | 4 | CF_RESET_MC
ATTRIBUTES | 2156135218 | 0
OUTPUTMC | 1 | 1 | 0
INPUTS | 13 | DATA<1>.PIN  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | RESET_OUTn
INPUTP | 13 | 1 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 133
EQ | 5 | 
   CF_RESET := DATA<1>.PIN;
    CF_RESET.CLK = !(ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	!ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8>);
    CF_RESET.AR = !RESET_OUTn;

MACROCELL | 4 | 1 | CPLD_INTn_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 27 | CF_IN_INT  | CF_OUT_INT  | MMC_IN_INT  | MMC_OUT_INT  | SIM_IN_INT  | SIM_OUT_INT  | USB_IN_INT  | USB_OUT_INT  | BCR2_REG<9>  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | _n002215  | SW1_INT  | SW2_INT  | SW3_INT  | SW4_1INT  | SW4_2INT  | SW4_3INT
INPUTMC | 16 | 0 | 15 | 5 | 9 | 4 | 14 | 4 | 15 | 2 | 9 | 2 | 7 | 7 | 14 | 8 | 15 | 10 | 4 | 3 | 2 | 5 | 10 | 3 | 11 | 3 | 5 | 6 | 9 | 6 | 8 | 7 | 15
INPUTP | 11 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169
EQ | 10 | 
   CPLD_INTn = !CF_IN_INT * !CF_OUT_INT * !MMC_IN_INT * 
	!MMC_OUT_INT * !SIM_IN_INT * !SIM_OUT_INT * !USB_IN_INT * 
	!USB_OUT_INT * BCR2_REG<9>
	# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !_n002215
	# !CF_IN_INT * !CF_OUT_INT * !MMC_IN_INT * 
	!MMC_OUT_INT * !SIM_IN_INT * !SIM_OUT_INT * !SW1_INT * !SW2_INT * 
	!SW3_INT * !SW4_1INT * !SW4_2INT * !SW4_3INT * !USB_IN_INT * 
	!USB_OUT_INT;

MACROCELL | 0 | 15 | CF_IN_INT_MC
ATTRIBUTES | 2172650288 | 0
OUTPUTMC | 2 | 4 | 1 | 2 | 2
INPUTS | 15 | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<6>.PIN  | CF_CD2n  | CF_CD1n  | CF_IN_INT__n0000
INPUTMC | 1 | 0 | 14
INPUTP | 14 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 206 | 109 | 112
LCT | 1 | 1 | Internal_Name
EQ | 8 | 
   !CF_IN_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<6>.PIN;
    CF_IN_INT.CLK = !CF_CD2n * !CF_CD1n;
    CF_IN_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * DATA<6>.PIN;
    CF_IN_INT.AR = CF_IN_INT__n0000;

MACROCELL | 0 | 14 | CF_IN_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
OUTPUTMC | 1 | 0 | 15
INPUTS | 13 | RESET_OUTn  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<6>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 206
EQ | 4 | 
   CF_IN_INT__n0000 = !RESET_OUTn
	# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<6>.PIN;

MACROCELL | 5 | 9 | CF_OUT_INT_MC
ATTRIBUTES | 2189427616 | 0
OUTPUTMC | 2 | 4 | 1 | 1 | 3
INPUTS | 14 | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<7>.PIN  | CF_CD2n  | CF_CD1n
INPUTP | 14 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 4 | 109 | 112
LCT | 1 | 4 | Internal_Name
EQ | 8 | 
   !CF_OUT_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<7>.PIN;
    CF_OUT_INT.CLK = !(!CF_CD2n * !CF_CD1n);
    CF_OUT_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * DATA<7>.PIN;
    CF_OUT_INT.AR = CF_OUT_INT__n0000;

MACROCELL | 0 | 10 | CF_OUT_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
INPUTS | 13 | RESET_OUTn  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<7>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 4
EQ | 4 | 
   CF_OUT_INT__n0000 = !RESET_OUTn
	# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<7>.PIN;

MACROCELL | 4 | 14 | MMC_IN_INT_MC
ATTRIBUTES | 2323645312 | 0
OUTPUTMC | 2 | 4 | 1 | 0 | 2
INPUTS | 12 | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<0>.PIN
INPUTP | 12 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 218
LCT | 2 | 4 | Internal_Name | 2 | Internal_Name
EQ | 8 | 
   !MMC_IN_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<0>.PIN;
    MMC_IN_INT.CLK = MMC_DETECT;
    MMC_IN_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * DATA<0>.PIN;
    MMC_IN_INT.AR = MMC_IN_INT__n0000;

MACROCELL | 2 | 14 | MMC_IN_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
INPUTS | 13 | RESET_OUTn  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<0>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 218
EQ | 4 | 
   MMC_IN_INT__n0000 = !RESET_OUTn
	# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<0>.PIN;

MACROCELL | 4 | 15 | MMC_OUT_INT_MC
ATTRIBUTES | 2306867984 | 0
OUTPUTMC | 2 | 4 | 1 | 1 | 0
INPUTS | 13 | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<1>.PIN  | MMC_OUT_INT__n0000
INPUTMC | 1 | 2 | 11
INPUTP | 12 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 1
LCT | 2 | 1 | Internal_Name | 2 | Internal_Name
EQ | 8 | 
   !MMC_OUT_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<1>.PIN;
    MMC_OUT_INT.CLK = !(MMC_DETECT);
    MMC_OUT_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * DATA<1>.PIN;
    MMC_OUT_INT.AR = MMC_OUT_INT__n0000;

MACROCELL | 2 | 11 | MMC_OUT_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
OUTPUTMC | 1 | 4 | 15
INPUTS | 13 | RESET_OUTn  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<1>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 1
EQ | 4 | 
   MMC_OUT_INT__n0000 = !RESET_OUTn
	# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<1>.PIN;

MACROCELL | 2 | 9 | SIM_IN_INT_MC
ATTRIBUTES | 2189427616 | 0
OUTPUTMC | 2 | 4 | 1 | 1 | 12
INPUTS | 13 | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<2>.PIN  | SIM_DETECTn
INPUTP | 13 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 8 | 134
LCT | 1 | 4 | Internal_Name
EQ | 8 | 
   !SIM_IN_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<2>.PIN;
    SIM_IN_INT.CLK = !(SIM_DETECTn);
    SIM_IN_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * DATA<2>.PIN;
    SIM_IN_INT.AR = SIM_IN_INT__n0000;

MACROCELL | 2 | 10 | SIM_IN_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
INPUTS | 13 | RESET_OUTn  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<2>.PIN
INPUTP | 13 | 133 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 8
EQ | 4 | 
   SIM_IN_INT__n0000 = !RESET_OUTn
	# ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<2>.PIN;

MACROCELL | 2 | 7 | SIM_OUT_INT_MC
ATTRIBUTES | 2172650288 | 0
OUTPUTMC | 2 | 4 | 1 | 1 | 13
INPUTS | 14 | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<3>.PIN  | SIM_DETECTn  | SIM_OUT_INT__n0000
INPUTMC | 1 | 2 | 8
INPUTP | 13 | 17 | 158 | 161 | 175 | 21 | 20 | 19 | 18 | 168 | 23 | 169 | 10 | 134
LCT | 1 | 1 | Internal_Name
EQ | 8 | 
   !SIM_OUT_INT := ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * !DATA<3>.PIN;
    SIM_OUT_INT.CLK = SIM_DETECTn;
    SIM_OUT_INT.AP = ADDR25 * !WEn * !RD_WRn * !CS2n * !ADDR<5> * 
	ADDR<4> * !ADDR<3> * !ADDR<2> * !ADDR<7> * !ADDR<6> * 
	!ADDR<8> * DATA<3>.PIN;
    SIM_OUT_INT.AR = SIM_OUT_INT__n0000;

MACROCELL | 2 | 8 | SIM_OUT_INT__n0000_MC
ATTRIBUTES | 536871680 | 0
OUTPUTMC | 1 | 2 | 7
INPUTS | 13 | RESET_OUTn  | ADDR25  | WEn  | RD_WRn  | CS2n  | ADDR<5>  | ADDR<4>  | ADDR<3>  | ADDR<2>  | ADDR<7>  | ADDR<6>  | ADDR<8>  | DATA<3>.PIN