pld01a.rpt
来自「Liod平台CPLD源代码 pxa270」· RPT 代码 · 共 971 行 · 第 1/5 页
RPT
971 行
BCR2_REG<7> XXXXXXXXX.XXXX.......................... 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB11 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 13
Number of function block inputs used/remaining: 13/27
Number of function block control terms used/remaining: 2/2
Number of PLA product terms used/remaining: 3/53
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB11_1 (b)
(unused) 0 FB11_2 (b)
(unused) 0 FB11_3 (b)
(unused) 0 FB11_4 (b)
BCR2_REG<9> 3 FB11_5 120 I/O (b)
(unused) 0 FB11_6 121 I/O
(unused) 0 FB11_7 (b)
(unused) 0 FB11_8 (b)
(unused) 0 FB11_9 (b)
(unused) 0 FB11_10 (b)
(unused) 0 FB11_11 124 I/O
(unused) 0 FB11_12 125 I/O
(unused) 0 FB11_13 126 I/O
(unused) 0 FB11_14 128 I/O
(unused) 0 FB11_15 129 I/O
(unused) 0 FB11_16 130 I/O
Signals Used by Logic in Function Block
1: ADDR25 6: ADDR<6> 10: DATA<9>.PIN
2: ADDR<2> 7: ADDR<7> 11: RD_WRn
3: ADDR<3> 8: ADDR<8> 12: RESET_OUTn
4: ADDR<4> 9: CS2n 13: WEn
5: ADDR<5>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
BCR2_REG<9> XXXXXXXXXXXXX........................... 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB12 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 0
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB12_1 (b)
(unused) 0 FB12_2 100 I/O
(unused) 0 FB12_3 (b)
(unused) 0 FB12_4 (b)
(unused) 0 FB12_5 (b)
(unused) 0 FB12_6 (b)
(unused) 0 FB12_7 (b)
(unused) 0 FB12_8 (b)
(unused) 0 FB12_9 (b)
(unused) 0 FB12_10 (b)
(unused) 0 FB12_11 98 I/O
(unused) 0 FB12_12 97 I/O
(unused) 0 FB12_13 96 I/O
(unused) 0 FB12_14 95 I/O
(unused) 0 FB12_15 94 I/O
(unused) 0 FB12_16 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB13 ***********************************
This function block is part of I/O Bank number: 1
Number of signals used by logic mapping into function block: 10
Number of function block inputs used/remaining: 10/30
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 6/50
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
CF_PWR_EN 1 FB13_1 75 I/O O
USB_IDE_CSn 1 FB13_2 76 I/O O
ADDR_DIRn 1 FB13_3 77 I/O O
(unused) 0 FB13_4 (b)
MMC_PWR_EN 1 FB13_5 78 I/O O
MS_PULL 1 FB13_6 79 I/O O
(unused) 0 FB13_7 (b)
(unused) 0 FB13_8 (b)
(unused) 0 FB13_9 (b)
(unused) 0 FB13_10 (b)
(unused) 0 FB13_11 (b)
MS_PWR_EN 1 FB13_12 80 I/O O
(unused) 0 FB13_13 81 I/O I
(unused) 0 FB13_14 82 I/O I
(unused) 0 FB13_15 (b)
(unused) 0 FB13_16 (b)
Signals Used by Logic in Function Block
1: BCR2_REG<0> 5: DATA<0> 8: MBGNT
2: CF_CD1n 6: DATA<15> 9: MMC_DETECT
3: CF_CD2n 7: DATA<4> 10: MSINS
4: CS4n
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
CF_PWR_EN .XX.X................................... 3 3
USB_IDE_CSn ...X.................................... 1 1
ADDR_DIRn ......XX................................ 2 2
MMC_PWR_EN .....X..X............................... 2 2
MS_PULL .....X..X............................... 2 2
MS_PWR_EN X........X.............................. 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB14 ***********************************
This function block is part of I/O Bank number: 1
Number of signals used by logic mapping into function block: 0
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB14_1 74 I/O I
(unused) 0 FB14_2 71 I/O I
(unused) 0 FB14_3 70 I/O I
(unused) 0 FB14_4 69 I/O I
(unused) 0 FB14_5 (b)
(unused) 0 FB14_6 68 I/O I
(unused) 0 FB14_7 (b)
(unused) 0 FB14_8 (b)
(unused) 0 FB14_9 (b)
(unused) 0 FB14_10 (b)
(unused) 0 FB14_11 (b)
(unused) 0 FB14_12 (b)
(unused) 0 FB14_13 66 I/O I
(unused) 0 FB14_14 64 I/O I
(unused) 0 FB14_15 (b)
(unused) 0 FB14_16 61 I/O I
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB15 ***********************************
This function block is part of I/O Bank number: 1
Number of signals used by logic mapping into function block: 0
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB15_1 (b)
(unused) 0 FB15_2 83 I/O I
(unused) 0 FB15_3 (b)
(unused) 0 FB15_4 (b)
(unused) 0 FB15_5 (b)
(unused) 0 FB15_6 (b)
(unused) 0 FB15_7 (b)
(unused) 0 FB15_8 (b)
(unused) 0 FB15_9 (b)
(unused) 0 FB15_10 (b)
(unused) 0 FB15_11 85 I/O I
(unused) 0 FB15_12 86 I/O I
(unused) 0 FB15_13 87 I/O I
(unused) 0 FB15_14 88 I/O I
(unused) 0 FB15_15 91 I/O I
(unused) 0 FB15_16 92 I/O I
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB16 ***********************************
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