pld01a.rpt
来自「Liod平台CPLD源代码 pxa270」· RPT 代码 · 共 971 行 · 第 1/5 页
RPT
971 行
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB7 ***********************************
This function block is part of I/O Bank number: 1
Number of signals used by logic mapping into function block: 24
Number of function block inputs used/remaining: 24/16
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 25/31
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB7_1 (b)
(unused) 0 FB7_2 (b)
(unused) 0 FB7_3 (b)
(unused) 0 FB7_4 (b)
IRDA_MD0 3 FB7_5 26 I/O O
IRDA_MD1 3 FB7_6 25 I/O O
(unused) 0 FB7_7 (b)
(unused) 0 FB7_8 (b)
SW4_2INT 4 FB7_9 (b) (b)
SW4_1INT 4 FB7_10 (b) (b)
LED_GREENn 3 FB7_11 24 I/O O
LED_REDn 3 FB7_12 23 I/O O
PSKTSEL 3 FB7_13 22 I/O O
RS232_ON 3 FB7_14 21 I/O O
SLEEPn 3 FB7_15 20 I/O O
SPKR_OFF 3 FB7_16 19 I/O O
Signals Used by Logic in Function Block
1: ADDR25 9: CS2n 17: DATA<9>.PIN
2: ADDR<2> 10: DATA<10>.PIN 18: RD_WRn
3: ADDR<3> 11: DATA<11>.PIN 19: RESET_OUTn
4: ADDR<4> 12: DATA<12>.PIN 20: SW4_1INT__n0000
5: ADDR<5> 13: DATA<13>.PIN 21: SW4_1
6: ADDR<6> 14: DATA<14>.PIN 22: SW4_2INT__n0000
7: ADDR<7> 15: DATA<3>.PIN 23: SW4_2
8: ADDR<8> 16: DATA<4>.PIN 24: WEn
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
IRDA_MD0 XXXXXXXXX.....X..XX....X................ 13 13
IRDA_MD1 XXXXXXXXX......X.XX....X................ 13 13
SW4_2INT XXXXXXXXX..X.....X...XXX................ 14 14
SW4_1INT XXXXXXXXX.X......X.XX..X................ 14 14
LED_GREENn XXXXXXXXX...X....XX....X................ 13 13
LED_REDn XXXXXXXXX..X.....XX....X................ 13 13
PSKTSEL XXXXXXXXXX.......XX....X................ 13 13
RS232_ON XXXXXXXXX.......XXX....X................ 13 13
SLEEPn XXXXXXXXX.X......XX....X................ 13 13
SPKR_OFF XXXXXXXXX....X...XX....X................ 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB8 ***********************************
This function block is part of I/O Bank number: 1
Number of signals used by logic mapping into function block: 21
Number of function block inputs used/remaining: 21/19
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 16/40
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
VGA_I2C_ENn 3 FB8_1 44 I/O O
EX_REG_CSn 1 FB8_2 45 I/O O
LAN_RESET 1 FB8_3 46 I/O O
(unused) 0 FB8_4 (b)
USB_IDE_RESn 1 FB8_5 48 I/O O
ADDR_OEn 0 FB8_6 49 I/O O
(unused) 0 FB8_7 (b)
(unused) 0 FB8_8 (b)
(unused) 0 FB8_9 (b)
(unused) 0 FB8_10 (b)
DATA_OEn 0 FB8_11 50 I/O O
LAN_AEN 1 FB8_12 51 I/O O
TX_OUT1 1 FB8_13 52 I/O O
(unused) 0 FB8_14 (b)
USB_IN_INT 4 FB8_15 (b) (b)
SW4_3INT 4 FB8_16 (b) (b)
Signals Used by Logic in Function Block
1: ADDR25 8: ADDR<8> 15: RESET_OUTn
2: ADDR<2> 9: CS2n 16: SW4_3INT__n0000
3: ADDR<3> 10: CS3n 17: SW4_3
4: ADDR<4> 11: DATA<13>.PIN 18: TX_IN1
5: ADDR<5> 12: DATA<2>.PIN 19: USB1_WAKE
6: ADDR<6> 13: DATA<4>.PIN 20: USB_IN_INT__n0000
7: ADDR<7> 14: RD_WRn 21: WEn
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
VGA_I2C_ENn XXXXXXXXX..X.XX.....X................... 13 13
EX_REG_CSn X.......X............................... 2 2
LAN_RESET ..............X......................... 1 1
USB_IDE_RESn ..............X......................... 1 1
ADDR_OEn ........................................ 0 0
DATA_OEn ........................................ 0 0
LAN_AEN .........X.............................. 1 1
TX_OUT1 .................X...................... 1 1
USB_IN_INT XXXXXXXXX...XX....XXX................... 14 14
SW4_3INT XXXXXXXXX.X..X.XX...X................... 14 14
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB9 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 14
Number of function block inputs used/remaining: 14/26
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 4/52
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB9_1 112 I/O I
(unused) 0 FB9_2 113 I/O I
(unused) 0 FB9_3 (b)
(unused) 0 FB9_4 114 I/O I
(unused) 0 FB9_5 (b)
(unused) 0 FB9_6 115 I/O I
(unused) 0 FB9_7 (b)
(unused) 0 FB9_8 (b)
(unused) 0 FB9_9 (b)
(unused) 0 FB9_10 (b)
(unused) 0 FB9_11 (b)
(unused) 0 FB9_12 116 I/O I
(unused) 0 FB9_13 117 I/O I
(unused) 0 FB9_14 118 I/O I
(unused) 0 FB9_15 119 I/O I
USB_OUT_INT 4 FB9_16 (b) (b)
Signals Used by Logic in Function Block
1: ADDR25 6: ADDR<6> 11: RD_WRn
2: ADDR<2> 7: ADDR<7> 12: USB1_WAKE
3: ADDR<3> 8: ADDR<8> 13: USB_OUT_INT__n0000
4: ADDR<4> 9: CS2n 14: WEn
5: ADDR<5> 10: DATA<5>.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
USB_OUT_INT XXXXXXXXXXXXXX.......................... 14 14
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB10 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 14
Number of function block inputs used/remaining: 14/26
Number of function block control terms used/remaining: 2/2
Number of PLA product terms used/remaining: 4/52
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB10_1 111 I/O I
(unused) 0 FB10_2 110 I/O I
(unused) 0 FB10_3 107 I/O I
(unused) 0 FB10_4 106 I/O I
(unused) 0 FB10_5 105 I/O I
(unused) 0 FB10_6 104 I/O I
(unused) 0 FB10_7 (b)
(unused) 0 FB10_8 (b)
(unused) 0 FB10_9 (b)
(unused) 0 FB10_10 (b)
(unused) 0 FB10_11 (b)
(unused) 0 FB10_12 103 I/O I
(unused) 0 FB10_13 (b)
BCR2_REG<12> 3 FB10_14 102 I/O (b)
(unused) 0 FB10_15 (b)
BCR2_REG<7> 3 FB10_16 101 I/O (b)
Signals Used by Logic in Function Block
1: ADDR25 6: ADDR<6> 11: DATA<7>.PIN
2: ADDR<2> 7: ADDR<7> 12: RD_WRn
3: ADDR<3> 8: ADDR<8> 13: RESET_OUTn
4: ADDR<4> 9: CS2n 14: WEn
5: ADDR<5> 10: DATA<12>.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
BCR2_REG<12> XXXXXXXXXX.XXX.......................... 13 13
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