pld01a.rpt
来自「Liod平台CPLD源代码 pxa270」· RPT 代码 · 共 971 行 · 第 1/5 页
RPT
971 行
SIM_OUT_INT XXXXXXXX....X....X.........X.X.X....X... 14 14
SIM_OUT_INT__n0000
XXXXXXXX....X....X.........XX.......X... 13 13
SIM_IN_INT XXXXXXXX....X...X..........X.XX.....X... 14 14
SIM_IN_INT__n0000
XXXXXXXX....X...X..........XX.......X... 13 13
MMC_OUT_INT__n0000
XXXXXXXX....X..X...........XX.......X... 13 13
BCR2_REG<0> XXXXXXXX....X.X............XX.......X... 13 13
SYS_CS0n .............X.......................... 1 1
MMC_IN_INT__n0000
XXXXXXXX....X.X............XX.......X... 13 13
SYS_CS1n ...........X............................ 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB4 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 35
Number of function block inputs used/remaining: 35/5
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 24/32
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
FLASH_RSTn 1 FB4_1 11 I/O O
TX_OUT0 1 FB4_2 12 I/O O
_n002215 1 FB4_3 13 I/O I
N_PZ_261 1 FB4_4 14 I/O I
_n0051 2 FB4_5 15 I/O I
SW3_INT 4 FB4_6 16 I/O I
BCR2_REG<5> 3 FB4_7 (b) (b)
USB_OUT_INT__n0000 2 FB4_8 (b) (b)
USB_IN_INT__n0000 2 FB4_9 (b) (b)
SW4_3INT__n0000 2 FB4_10 (b) (b)
SW4_2INT__n0000 2 FB4_11 (b) (b)
SW2_INT 4 FB4_12 17 I/O I
SW4_1INT__n0000 2 FB4_13 (b) (b)
BCR2_REG<15> 3 FB4_14 18 I/O I
SW3_INT__n0000 2 FB4_15 (b) (b)
SW2_INT__n0000 2 FB4_16 (b) (b)
Signals Used by Logic in Function Block
1: ADDR25 13: DATA<12>.PIN 25: DATA<9>.PIN
2: ADDR<2> 14: DATA<13>.PIN 26: N_PZ_261
3: ADDR<3> 15: DATA<14>.PIN 27: OEn
4: ADDR<4> 16: DATA<15>.PIN 28: RD_WRn
5: ADDR<5> 17: DATA<1>.PIN 29: RESET_OUTn
6: ADDR<6> 18: DATA<2>.PIN 30: SW2
7: ADDR<7> 19: DATA<3>.PIN 31: SW2_INT__n0000
8: ADDR<8> 20: DATA<4>.PIN 32: SW3
9: CS2n 21: DATA<5>.PIN 33: SW3_INT__n0000
10: DATA<0>.PIN 22: DATA<6>.PIN 34: TX_IN0
11: DATA<10>.PIN 23: DATA<7>.PIN 35: WEn
12: DATA<11>.PIN 24: DATA<8>.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
FLASH_RSTn ............................X........... 1 1
TX_OUT0 .................................X...... 1 1
_n002215 .........XXXXXXXXXXXXXXXX............... 16 16
N_PZ_261 X..XXXXXX.................XX............ 9 9
_n0051 XXX.XXXXX................XXX............ 11 11
SW3_INT XXXXXXXXX.X................X...XX.X..... 14 14
BCR2_REG<5> XXXXXXXXX...........X......XX.....X..... 13 13
USB_OUT_INT__n0000
XXXXXXXXX...........X......XX.....X..... 13 13
USB_IN_INT__n0000
XXXXXXXXX..........X.......XX.....X..... 13 13
SW4_3INT__n0000 XXXXXXXXX....X.............XX.....X..... 13 13
SW4_2INT__n0000 XXXXXXXXX...X..............XX.....X..... 13 13
SW2_INT XXXXXXXXX...............X..X.XX...X..... 14 14
SW4_1INT__n0000 XXXXXXXXX..X...............XX.....X..... 13 13
BCR2_REG<15> XXXXXXXXX......X...........XX.....X..... 13 13
SW3_INT__n0000 XXXXXXXXX.X................XX.....X..... 13 13
SW2_INT__n0000 XXXXXXXXX...............X..XX.....X..... 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB5 ***********************************
This function block is part of I/O Bank number: 1
Number of signals used by logic mapping into function block: 35
Number of function block inputs used/remaining: 35/5
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 21/35
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB5_1 (b)
CPLD_INTn 3 FB5_2 33 I/O O
(unused) 0 FB5_3 (b)
AUDIO_PWR_EN 3 FB5_4 32 GCK/I/O O
CF_RESET 3 FB5_5 31 I/O O
VBUS1_ON 3 FB5_6 30 GCK/I/O O
(unused) 0 FB5_7 (b)
(unused) 0 FB5_8 (b)
(unused) 0 FB5_9 (b)
(unused) 0 FB5_10 (b)
(unused) 0 FB5_11 (b)
(unused) 0 FB5_12 (b)
(unused) 0 FB5_13 (b)
DAC_PWR_EN 3 FB5_14 28 I/O O
MMC_IN_INT 4 FB5_15 (b) (b)
MMC_OUT_INT 4 FB5_16 (b) (b)
Signals Used by Logic in Function Block
1: ADDR25 13: DATA<0>.PIN 25: SIM_OUT_INT
2: ADDR<2> 14: DATA<1>.PIN 26: SW1_INT
3: ADDR<3> 15: DATA<3>.PIN 27: SW2_INT
4: ADDR<4> 16: DATA<6>.PIN 28: SW3_INT
5: ADDR<5> 17: MMC_DETECT 29: SW4_1INT
6: ADDR<6> 18: MMC_IN_INT 30: SW4_2INT
7: ADDR<7> 19: MMC_IN_INT__n0000 31: SW4_3INT
8: ADDR<8> 20: MMC_OUT_INT 32: USB_IN_INT
9: BCR2_REG<9> 21: MMC_OUT_INT__n0000
33: USB_OUT_INT
10: CF_IN_INT 22: RD_WRn 34: WEn
11: CF_OUT_INT 23: RESET_OUTn 35: _n002215
12: CS2n 24: SIM_IN_INT
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
CPLD_INTn XXXXXXXXXXXX.....X.X.X.XXXXXXXXXXXX..... 27 27
AUDIO_PWR_EN XXXXXXXX...X...X.....XX..........X...... 13 13
CF_RESET XXXXXXXX...X.X.......XX..........X...... 13 13
VBUS1_ON XXXXXXXX...X.X.......XX..........X...... 13 13
DAC_PWR_EN XXXXXXXX...X..X......XX..........X...... 13 13
MMC_IN_INT XXXXXXXX...XX...X.X..X...........X...... 14 14
MMC_OUT_INT XXXXXXXX...X.X..X...XX...........X...... 14 14
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB6 ***********************************
This function block is part of I/O Bank number: 1
Number of signals used by logic mapping into function block: 31
Number of function block inputs used/remaining: 31/9
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 30/26
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
DATA_DIRn 9 FB6_1 34 I/O O
EX_FLASH_CSn 1 FB6_2 35 CDR/I/O O
(unused) 0 FB6_3 (b)
CF_OEn 2 FB6_4 38 GCK/I/O O
(unused) 0 FB6_5 (b)
(unused) 0 FB6_6 (b)
(unused) 0 FB6_7 (b)
(unused) 0 FB6_8 (b)
(unused) 0 FB6_9 (b)
CF_OUT_INT 4 FB6_10 (b) (b)
SW1_INT 4 FB6_11 (b) (b)
EX_OUT0 1 FB6_12 39 DGE/I/O O
HDD_PWR_EN 3 FB6_13 40 I/O O
EX_OUT1 3 FB6_14 41 I/O O
LCD_PWR_ON 3 FB6_15 42 I/O O
IRDA_FSEL 3 FB6_16 43 I/O O
Signals Used by Logic in Function Block
1: ADDR25 12: CF_OUT_INT__n0000 22: DVAL1
2: ADDR<2> 13: CS0n 23: OEn
3: ADDR<3> 14: CS2n 24: PCE1n
4: ADDR<4> 15: CS3n 25: PCE2n
5: ADDR<5> 16: CS4n 26: RD_WRn
6: ADDR<6> 17: DATA<2>.PIN 27: RESET_OUTn
7: ADDR<7> 18: DATA<4> 28: SW1
8: ADDR<8> 19: DATA<5> 29: SW1_INT__n0000
9: BCR2_REG<5> 20: DATA<7>.PIN 30: SWAP_FLASH
10: CF_CD1n 21: DATA<8>.PIN 31: WEn
11: CF_CD2n
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DATA_DIRn X.......X...XXXX.X...XXXXX...X.......... 13 13
EX_FLASH_CSn ............X................X.......... 2 2
CF_OEn ..................X....XX............... 3 3
CF_OUT_INT XXXXXXXX.XXX.X.....X.....X....X......... 15 15
SW1_INT XXXXXXXX.....X......X....X.XX.X......... 14 14
EX_OUT0 X............X.......................... 2 2
HDD_PWR_EN XXXXXXXX.....X.....X.....XX...X......... 13 13
EX_OUT1 XXXXXXXX.....X......X....XX...X......... 13 13
LCD_PWR_ON XXXXXXXX.....X......X....XX...X......... 13 13
IRDA_FSEL XXXXXXXX.....X..X........XX...X......... 13 13
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