pld01a.rpt
来自「Liod平台CPLD源代码 pxa270」· RPT 代码 · 共 971 行 · 第 1/5 页
RPT
971 行
- DG - DataGate
Reg Use - LATCH - Transparent latch
- DFF - D-flip-flop
- DEFF - D-flip-flop with clock enable
- TFF - T-flip-flop
- TDFF - Dual-edge-triggered T-flip-flop
- DDFF - Dual-edge-triggered flip-flop
- DDEFF - Dual-edge-triggered flip-flop with clock enable
/S (after any above flop/latch type) indicates initial state is Set
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 9 38 38 30 0/6 6
FB2 8 36 36 33 1/7 8
FB3 14 38 38 37 3/3 6
FB4 16 35 35 24 2/0 8
FB5 7 35 35 21 5/0 5
FB6 10 31 31 30 8/0 8
FB7 10 24 24 25 8/0 8
FB8 10 21 21 16 8/0 8
FB9 1 14 14 4 0/0 8
FB10 2 14 14 4 0/0 9
FB11 1 13 13 3 0/0 8
FB12 0 0 0 0 0/0 6
FB13 6 10 10 6 6/0 8
FB14 0 0 0 0 0/0 8
FB15 0 0 0 0 0/0 7
FB16 0 0 0 0 0/0 7
---- ----- ----- -----
94 233 41/16 118
*********************************** FB1 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 38
Number of function block inputs used/remaining: 38/2
Number of function block control terms used/remaining: 4/0
Number of PLA product terms used/remaining: 30/26
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB1_1 (b)
(unused) 0 FB1_2 (b)
DATA<0> 8 FB1_3 143 GSR/I/O I/O
DATA<14> 5 FB1_4 142 I/O I/O
(unused) 0 FB1_5 (b)
DATA<15> 5 FB1_6 140 I/O I/O
(unused) 0 FB1_7 (b)
(unused) 0 FB1_8 (b)
(unused) 0 FB1_9 (b)
(unused) 0 FB1_10 (b)
CF_OUT_INT__n0000 2 FB1_11 (b) (b)
DATA<13> 6 FB1_12 139 I/O I/O
DATA<10> 7 FB1_13 138 I/O I/O
DATA<11> 7 FB1_14 137 I/O I/O
CF_IN_INT__n0000 2 FB1_15 (b) (b)
CF_IN_INT 4 FB1_16 (b) (b)
Signals Used by Logic in Function Block
1: ADDR25 14: CS2n 27: N_PZ_261
2: ADDR<2> 15: DATA<0> 28: PSKTSEL
3: ADDR<3> 16: DATA<10> 29: RD_WRn
4: ADDR<4> 17: DATA<11> 30: RESET_OUTn
5: ADDR<5> 18: DATA<13> 31: SLEEPn
6: ADDR<6> 19: DATA<14> 32: SPKR_OFF
7: ADDR<7> 20: DATA<15> 33: SW1
8: ADDR<8> 21: DATA<6>.PIN 34: SW3_INT
9: BCR2_REG<0> 22: DATA<7>.PIN 35: SW4_1INT
10: BCR2_REG<15> 23: EXB_PRESn 36: SW4_3INT
11: CF_CD1n 24: EX_IN0 37: WEn
12: CF_CD2n 25: LED_GREENn 38: _n0051
13: CF_IN_INT__n0000 26: MMC_IN_INT
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DATA<0> XXXXXXXXX.XX.XX..........XX.XX..X...XX.. 20 20
DATA<14> XXXXXXXX.....X....X.......X.XX.X....XX.. 16 16
DATA<15> XXXXXXXX.X...X.....X......X.XX......XX.. 16 16
CF_OUT_INT__n0000
XXXXXXXX.....X.......X......XX......X... 13 13
DATA<13> XXXXXXXX.....X...X......X.X.XX.....XXX.. 17 17
DATA<10> XXXXXXXX.....X.X......X...XXXX...X..XX.. 18 18
DATA<11> XXXXXXXX.....X..X......X..X.XXX...X.XX.. 18 18
CF_IN_INT__n0000 XXXXXXXX.....X......X.......XX......X... 13 13
CF_IN_INT XXXXXXXX..XXXX......X.......X.......X... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB2 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 36
Number of function block inputs used/remaining: 36/4
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 33/23
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
DATA<1> 6 FB2_1 2 GTS/I/O I/O
(unused) 0 FB2_2 (b)
DATA<12> 5 FB2_3 3 GTS/I/O I/O
DATA<7> 5 FB2_4 4 I/O I/O
DATA<8> 5 FB2_5 5 GTS/I/O I/O
(unused) 0 FB2_6 (b)
(unused) 0 FB2_7 (b)
(unused) 0 FB2_8 (b)
(unused) 0 FB2_9 (b)
(unused) 0 FB2_10 (b)
(unused) 0 FB2_11 (b)
DATA<9> 5 FB2_12 6 GTS/I/O I/O
DATA<2> 6 FB2_13 7 I/O I/O
DATA<3> 6 FB2_14 9 I/O I/O
FLASH_CSn 1 FB2_15 10 I/O O
(unused) 0 FB2_16 (b)
Signals Used by Logic in Function Block
1: ADDR<2> 13: EX_OUT1 25: SIM_OUT_INT
2: ADDR<3> 14: HDD_PWR_EN 26: SW1_INT
3: BCR2_REG<12> 15: IRDA_FSEL 27: SW2
4: BCR2_REG<7> 16: IRDA_MD0 28: SW2_INT
5: BCR2_REG<9> 17: LCD_PWR_ON 29: SW3
6: CF_BVD1 18: LED_REDn 30: SW4_1
7: CF_BVD2 19: MMC_DETECT 31: SW4_2INT
8: CF_OUT_INT 20: MMC_OUT_INT 32: SWAP_FLASH
9: CF_RESET 21: N_PZ_261 33: USB1_WAKE
10: CS0n 22: POLL_FLAG 34: VBUS1_ON
11: DAC_PWR_EN 23: RS232_ON 35: VGA_I2C_ENn
12: EX_IN1 24: SIM_IN_INT 36: _n0051
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DATA<1> XX...X..X..........XX.....X......X.X.... 9 9
DATA<12> XXX........X.....X..X.........X....X.... 8 8
DATA<7> XX.X...X.....X......XX.............X.... 8 8
DATA<8> XX..........X...X...X....X......X..X.... 8 8
DATA<9> XX..X...............X.X....X...X...X.... 8 8
DATA<2> XX....X.......X.....X..X....X.....XX.... 9 9
DATA<3> XX........X....X..X.X...X....X.....X.... 9 9
FLASH_CSn .........X.....................X........ 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB3 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 38
Number of function block inputs used/remaining: 38/2
Number of function block control terms used/remaining: 4/0
Number of PLA product terms used/remaining: 37/19
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
DATA<4> 8 FB3_1 136 I/O I/O
DATA<5> 8 FB3_2 135 I/O I/O
DATA<6> 8 FB3_3 134 I/O I/O
(unused) 0 FB3_4 (b)
BRDY_ENn 1 FB3_5 133 I/O O
(unused) 0 FB3_6 (b)
SW1_INT__n0000 2 FB3_7 (b) (b)
SIM_OUT_INT 4 FB3_8 (b) (b)
SIM_OUT_INT__n0000 2 FB3_9 (b) (b)
SIM_IN_INT 4 FB3_10 (b) (b)
SIM_IN_INT__n0000 2 FB3_11 (b) (b)
MMC_OUT_INT__n0000 2 FB3_12 (b) (b)
BCR2_REG<0> 3 FB3_13 (b) (b)
SYS_CS0n 1 FB3_14 132 I/O O
MMC_IN_INT__n0000 2 FB3_15 (b) (b)
SYS_CS1n 1 FB3_16 131 I/O O
Signals Used by Logic in Function Block
1: ADDR25 14: CS5n 27: N_PZ_261
2: ADDR<2> 15: DATA<0>.PIN 28: RD_WRn
3: ADDR<3> 16: DATA<1>.PIN 29: RESET_OUTn
4: ADDR<4> 17: DATA<2>.PIN 30: SIM_DETECTn
5: ADDR<5> 18: DATA<3>.PIN 31: SIM_IN_INT__n0000
6: ADDR<6> 19: DATA<4> 32: SIM_OUT_INT__n0000
7: ADDR<7> 20: DATA<5> 33: SW4_2
8: ADDR<8> 21: DATA<6> 34: SW4_3
9: AUDIO_PWR_EN 22: DATA<8>.PIN 35: USB_IN_INT
10: BCR2_REG<5> 23: DIP_DATA 36: USB_OUT_INT
11: CF_IN_INT 24: IRDA_MD1 37: WEn
12: CS1n 25: MMC_WP 38: _n0051
13: CS2n 26: MSINS
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DATA<4> XXXXXXXX....X.....X....XX.XXX...X.X.XX.. 19 19
DATA<5> XXXXXXXX.X..X......X......XXXX...X.XXX.. 19 19
DATA<6> XXXXXXXXX.X.X.......X.X..XXXX.......XX.. 19 19
BRDY_ENn .............X.......................... 1 1
SW1_INT__n0000 XXXXXXXX....X........X.....XX.......X... 13 13
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