pld01a.rpt
来自「Liod平台CPLD源代码 pxa270」· RPT 代码 · 共 971 行 · 第 1/5 页
RPT
971 行
cpldfit: version G.28 Xilinx Inc.
Fitter Report
Design Name: pld01a Date: 6- 5-2006, 4:39PM
Device Used: XC2C256-7-TQ144
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
94 /256 ( 37%) 233 /896 ( 26%) 46 /256 ( 18%) 102/118 ( 86%) 309/640 ( 48%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 45 45 | I/O : 92 16
Output : 41 41 | GCK/IO : 3 0
Bidirectional : 16 16 | GTS/IO : 4 0
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 | CDR/IO : 1 0
GSR : 0 0 | DGE/IO : 1 0
---- ----
Total 102 102
MACROCELL RESOURCES:
Total Macrocells Available 256
Registered Macrocells 46
Non-registered Macrocell driving I/O 31
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Slew Pin Pin Pin Reg I/O I/O Reg Init
Name Pt Used Rate # Type Use Use STD Style State
ADDR_DIRn 1 2 FB13_3 FAST 77 I/O O LVCMOS33
ADDR_OEn 0 0 FB8_6 FAST 49 I/O O LVCMOS33
AUDIO_PWR_EN 3 13 FB5_4 FAST 32 GCK/I/O O DFF LVCMOS33 RESET
BCR2_REG<0> 3 13 FB3_13 (b) (b) DFF RESET
BCR2_REG<12> 3 13 FB10_14 102 I/O (b) DFF RESET
BCR2_REG<15> 3 13 FB4_14 18 I/O I DFF RESET
BCR2_REG<5> 3 13 FB4_7 (b) (b) DFF RESET
BCR2_REG<7> 3 13 FB10_16 101 I/O (b) DFF RESET
BCR2_REG<9> 3 13 FB11_5 120 I/O (b) DFF RESET
BRDY_ENn 1 1 FB3_5 FAST 133 I/O O LVCMOS18
CF_IN_INT 4 15 FB1_16 (b) (b) DFF RESET
CF_IN_INT__n0000 2 13 FB1_15 (b) (b)
CF_OEn 2 3 FB6_4 FAST 38 GCK/I/O O LVCMOS33
CF_OUT_INT 4 15 FB6_10 (b) (b) DFF RESET
CF_OUT_INT__n0000 2 13 FB1_11 (b) (b)
CF_PWR_EN 1 3 FB13_1 FAST 75 I/O O LVCMOS33
CF_RESET 3 13 FB5_5 FAST 31 I/O O DFF LVCMOS33 RESET
CPLD_INTn 3 27 FB5_2 FAST 33 I/O O LVCMOS33
DAC_PWR_EN 3 13 FB5_14 FAST 28 I/O O DFF LVCMOS33 RESET
DATA<0> 8 20 FB1_3 FAST 143 GSR/I/O I/O DFF LVCMOS18 KPR RESET
DATA<10> 7 18 FB1_13 FAST 138 I/O I/O DFF LVCMOS18 KPR RESET
DATA<11> 7 18 FB1_14 FAST 137 I/O I/O DFF LVCMOS18 KPR RESET
DATA<12> 5 8 FB2_3 FAST 3 GTS/I/O I/O LVCMOS18 KPR
DATA<13> 6 17 FB1_12 FAST 139 I/O I/O DFF LVCMOS18 KPR RESET
DATA<14> 5 16 FB1_4 FAST 142 I/O I/O DFF LVCMOS18 KPR RESET
DATA<15> 5 16 FB1_6 FAST 140 I/O I/O DFF LVCMOS18 KPR RESET
DATA<1> 6 9 FB2_1 FAST 2 GTS/I/O I/O LVCMOS18 KPR
DATA<2> 6 9 FB2_13 FAST 7 I/O I/O LVCMOS18 KPR
DATA<3> 6 9 FB2_14 FAST 9 I/O I/O LVCMOS18 KPR
DATA<4> 8 19 FB3_1 FAST 136 I/O I/O DFF LVCMOS18 KPR RESET
DATA<5> 8 19 FB3_2 FAST 135 I/O I/O DFF LVCMOS18 KPR RESET
DATA<6> 8 19 FB3_3 FAST 134 I/O I/O DFF LVCMOS18 KPR RESET
DATA<7> 5 8 FB2_4 FAST 4 I/O I/O LVCMOS18 KPR
DATA<8> 5 8 FB2_5 FAST 5 GTS/I/O I/O LVCMOS18 KPR
DATA<9> 5 8 FB2_12 FAST 6 GTS/I/O I/O LVCMOS18 KPR
DATA_DIRn 9 13 FB6_1 FAST 34 I/O O LVCMOS33
DATA_OEn 0 0 FB8_11 FAST 50 I/O O LVCMOS33
EX_FLASH_CSn 1 2 FB6_2 FAST 35 CDR/I/O O LVCMOS33
EX_OUT0 1 2 FB6_12 FAST 39 DGE/I/O O LVCMOS33
EX_OUT1 3 13 FB6_14 FAST 41 I/O O DFF LVCMOS33 RESET
EX_REG_CSn 1 2 FB8_2 FAST 45 I/O O LVCMOS33
FLASH_CSn 1 2 FB2_15 FAST 10 I/O O LVCMOS18
FLASH_RSTn 1 1 FB4_1 FAST 11 I/O O LVCMOS18
HDD_PWR_EN 3 13 FB6_13 FAST 40 I/O O DFF LVCMOS33 RESET
IRDA_FSEL 3 13 FB6_16 FAST 43 I/O O DFF LVCMOS33 RESET
IRDA_MD0 3 13 FB7_5 FAST 26 I/O O DFF LVCMOS33 RESET
IRDA_MD1 3 13 FB7_6 FAST 25 I/O O DFF LVCMOS33 RESET
LAN_AEN 1 1 FB8_12 FAST 51 I/O O LVCMOS33
LAN_RESET 1 1 FB8_3 FAST 46 I/O O LVCMOS33
LCD_PWR_ON 3 13 FB6_15 FAST 42 I/O O DFF LVCMOS33 RESET
LED_GREENn 3 13 FB7_11 FAST 24 I/O O DFF LVCMOS33 RESET
LED_REDn 3 13 FB7_12 FAST 23 I/O O DFF LVCMOS33 RESET
MMC_IN_INT 4 14 FB5_15 (b) (b) DFF RESET
MMC_IN_INT__n0000 2 13 FB3_15 (b) (b)
MMC_OUT_INT 4 14 FB5_16 (b) (b) DFF RESET
MMC_OUT_INT__n0000 2 13 FB3_12 (b) (b)
MMC_PWR_EN 1 2 FB13_5 FAST 78 I/O O LVCMOS33
MS_PULL 1 2 FB13_6 FAST 79 I/O O LVCMOS33
MS_PWR_EN 1 2 FB13_12 FAST 80 I/O O LVCMOS33
N_PZ_261 1 9 FB4_4 14 I/O I
PSKTSEL 3 13 FB7_13 FAST 22 I/O O DFF LVCMOS33 RESET
RS232_ON 3 13 FB7_14 FAST 21 I/O O DFF LVCMOS33 RESET
SIM_IN_INT 4 14 FB3_10 (b) (b) DFF RESET
SIM_IN_INT__n0000 2 13 FB3_11 (b) (b)
SIM_OUT_INT 4 14 FB3_8 (b) (b) DFF RESET
SIM_OUT_INT__n0000 2 13 FB3_9 (b) (b)
SLEEPn 3 13 FB7_15 FAST 20 I/O O DFF LVCMOS33 RESET
SPKR_OFF 3 13 FB7_16 FAST 19 I/O O DFF LVCMOS33 RESET
SW1_INT 4 14 FB6_11 (b) (b) DFF RESET
SW1_INT__n0000 2 13 FB3_7 (b) (b)
SW2_INT 4 14 FB4_12 17 I/O I DFF RESET
SW2_INT__n0000 2 13 FB4_16 (b) (b)
SW3_INT 4 14 FB4_6 16 I/O I DFF RESET
SW3_INT__n0000 2 13 FB4_15 (b) (b)
SW4_1INT 4 14 FB7_10 (b) (b) DFF RESET
SW4_1INT__n0000 2 13 FB4_13 (b) (b)
SW4_2INT 4 14 FB7_9 (b) (b) DFF RESET
SW4_2INT__n0000 2 13 FB4_11 (b) (b)
SW4_3INT 4 14 FB8_16 (b) (b) DFF RESET
SW4_3INT__n0000 2 13 FB4_10 (b) (b)
SYS_CS0n 1 1 FB3_14 FAST 132 I/O O LVCMOS18
SYS_CS1n 1 1 FB3_16 FAST 131 I/O O LVCMOS18
TX_OUT0 1 1 FB4_2 FAST 12 I/O O LVCMOS18
TX_OUT1 1 1 FB8_13 FAST 52 I/O O LVCMOS33
USB_IDE_CSn 1 1 FB13_2 FAST 76 I/O O LVCMOS33
USB_IDE_RESn 1 1 FB8_5 FAST 48 I/O O LVCMOS33
USB_IN_INT 4 14 FB8_15 (b) (b) DFF RESET
USB_IN_INT__n0000 2 13 FB4_9 (b) (b)
USB_OUT_INT 4 14 FB9_16 (b) (b) DFF RESET
USB_OUT_INT__n0000 2 13 FB4_8 (b) (b)
VBUS1_ON 3 13 FB5_6 FAST 30 GCK/I/O O DFF LVCMOS33 RESET
VGA_I2C_ENn 3 13 FB8_1 FAST 44 I/O O DFF LVCMOS33 RESET
_n002215 1 16 FB4_3 13 I/O I
_n0051 2 11 FB4_5 15 I/O I
** INPUTS **
Signal Loc Pin Pin Pin Reg I/O I/O
Name # Type Use Use STD Style
ADDR25 FB4_3 13 I/O I LVCMOS18 KPR
ADDR<2> FB4_4 14 I/O I LVCMOS18 KPR
ADDR<3> FB4_5 15 I/O I LVCMOS18 KPR
ADDR<4> FB4_6 16 I/O I LVCMOS18 KPR
ADDR<5> FB4_12 17 I/O I LVCMOS18 KPR
ADDR<6> FB4_14 18 I/O I LVCMOS18 KPR
ADDR<7> FB9_1 112 I/O I LVCMOS18 KPR
ADDR<8> FB9_2 113 I/O I LVCMOS18 KPR
CF_BVD1 FB13_13 81 I/O I LVCMOS33 KPR
CF_BVD2 FB13_14 82 I/O I LVCMOS33 KPR
CF_CD1n FB14_1 74 I/O I LVCMOS33 KPR
CF_CD2n FB14_2 71 I/O I LVCMOS33 KPR
CS0n FB9_4 114 I/O I LVCMOS18 KPR
CS1n FB9_6 115 I/O I LVCMOS18 KPR
CS2n FB9_12 116 I/O I LVCMOS18 KPR
CS3n FB9_13 117 I/O I LVCMOS18 KPR
CS4n FB9_14 118 I/O I LVCMOS18 KPR
CS5n FB9_15 119 I/O I LVCMOS18 KPR
DIP_DATA FB14_3 70 I/O I LVCMOS33 KPR
DVAL1 FB14_4 69 I/O I LVCMOS33 KPR
EXB_PRESn FB14_6 68 I/O I LVCMOS33 KPR
EX_IN0 FB14_13 66 I/O I LVCMOS33 KPR
EX_IN1 FB14_14 64 I/O I LVCMOS33 KPR
MBGNT FB10_1 111 I/O I LVCMOS18 KPR
MMC_DETECT FB14_16 61 I/O I LVCMOS33 KPR
MMC_WP FB15_2 83 I/O I LVCMOS33 KPR
MSINS FB15_11 85 I/O I LVCMOS33 KPR
OEn FB10_2 110 I/O I LVCMOS18 KPR
PCE1n FB10_3 107 I/O I LVCMOS18 KPR
PCE2n FB10_4 106 I/O I LVCMOS18 KPR
POLL_FLAG FB15_12 86 I/O I LVCMOS33 KPR
RD_WRn FB10_5 105 I/O I LVCMOS18 KPR
RESET_OUTn FB15_13 87 I/O I LVCMOS33 KPR
SIM_DETECTn FB15_14 88 I/O I LVCMOS33 KPR
SW1 FB15_15 91 I/O I LVCMOS33 KPR
SW2 FB15_16 92 I/O I LVCMOS33 KPR
SW3 FB16_5 60 I/O I LVCMOS33 KPR
SW4_1 FB16_6 59 I/O I LVCMOS33 KPR
SW4_2 FB16_11 58 I/O I LVCMOS33 KPR
SW4_3 FB16_12 57 I/O I LVCMOS33 KPR
SWAP_FLASH FB16_13 56 I/O I LVCMOS33 KPR
TX_IN0 FB10_6 104 I/O I LVCMOS18 KPR
TX_IN1 FB16_15 54 I/O I LVCMOS33 KPR
USB1_WAKE FB16_16 53 I/O I LVCMOS33 KPR
WEn FB10_12 103 I/O I LVCMOS18 KPR
End of Resources
Legend:
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
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